Invention Grant
- Patent Title: Stackable semiconductor chip layer comprising prefabricated trench interconnect vias
- Patent Title (中): 可堆叠半导体芯片层,包括预制沟槽互连通孔
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Application No.: US11150712Application Date: 2005-06-10
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Publication No.: US07786562B2Publication Date: 2010-08-31
- Inventor: Volkan Ozguz , Angel Pepe , James Yamaguchi , W. Eric Boyd , Douglas Albert , Andrew Camien
- Applicant: Volkan Ozguz , Angel Pepe , James Yamaguchi , W. Eric Boyd , Douglas Albert , Andrew Camien
- Main IPC: H01L23/02
- IPC: H01L23/02

Abstract:
A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations on each die on the wafer at the reticle level using a series of semiconductor processing steps. The wafer is passivated and the vias are filled with a conductive material. The bond pads on the die are exposed and a metallization reroute from the user-selected bond pads and vias is applied. The wafer is then segmented to form thin, stackable layers that can be stacked and vertically electrically interconnected using the conductive vias, forming high-density electronic modules which may, in turn, be further stacked and interconnected to form larger more complex stacks.
Public/Granted literature
- US20050277288A1 Stackable semiconductor chip layer comprising prefabricated trench interconnect vias Public/Granted day:2005-12-15
Information query
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