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    Method of manufacturing printed circuit board and multi-layered PCB
    1.
    发明授权
    Method of manufacturing printed circuit board and multi-layered PCB 失效
    制造印刷电路板和多层PCB的方法

    公开(公告)号：US06902660B2

    公开(公告)日：2005-06-07

    申请号：US10231052

    申请日：2002-08-30

    Applicant: Hyuek Jae Lee ,  Jin Yu

    Inventor： Hyuek Jae Lee ,  Jin Yu

    IPC: H05K3/00 ,  C25D5/02 ,  H05K3/20 ,  H05K3/38 ,  H05K3/42 ,  H05K3/46 ,  C25D1/00

    CPC classification number: H05K3/4617 ,  C25D5/02 ,  H05K3/205 ,  H05K3/384 ,  H05K3/423 ,  H05K2201/0154 ,  H05K2203/0733

    Abstract: Disclosed is a fabrication method of a printed circuit board, consisting of plating a metal on a pattern-formed metallic substrate to form a conductive metal line; forming a polymer layer as a base substrate over the conductive metal line-formed metallic substrate and drying the formed polymer layer; forming a via hole in the polymer layer, followed by plugging the formed via hole by electroplating; and removing the metallic substrate. The method is advantageous in terms of maximum efficiency of use of the surface area of PCB, and fineness and high integration of circuits because of not requiring an additional etching process.

    Abstract translation: 公开了一种印刷电路板的制造方法，其包括在图案形成的金属基板上镀金属以形成导电金属线; 在导电金属线形金属基材上形成聚合物层作为基底，干燥所形成的聚合物层; 在聚合物层中形成通孔，然后通过电镀将形成的通孔堵塞; 并去除金属基底。 该方法在PCB的表面积的最大使用效率以及电路的细度和高集成度方面是有利的，因为不需要另外的蚀刻工艺。

    Apparatus for controlling cycles of optical pulse stream based on time correlation
    3.
    发明授权
    Apparatus for controlling cycles of optical pulse stream based on time correlation 有权
    基于时间相关控制光脉冲周期的装置

    公开(公告)号：US06594053B1

    公开(公告)日：2003-07-15

    申请号：US09432392

    申请日：1999-11-02

    Applicant: Hyuek Jae Lee ,  Hae Geun Kim ,  Jee Yon Choi ,  Sung Wan Kim

    Inventor： Hyuek Jae Lee ,  Hae Geun Kim ,  Jee Yon Choi ,  Sung Wan Kim

    IPC: H04B1000

    CPC classification number: H04B10/299

    Abstract: An apparatus for controlling cycles of optical pulse streams based on a time correlation is disclosed. The feedback optical pulses and the input optical pulses are subjected to a time interleaving so as to make them not overlapped together, and then they are subjected to a time correlation, thereby considerably reducing the polarized beam dependence of the input optical pulse streams. The apparatus includes a clock generating means for generating clocks, and an optical pulse generating means for receiving the clocks from the clock generating means to generate optical pulses in synchronization with the pulses of the clock generating means. An input optical pulse distributing means distributes the feedback optical pulses of an output optical pulse distributing means, and distributes the optical pulses of the optical pulse generating means. A time correlation means correlates the time of optical pulses of the input optical pulse distributing means, and an optical pulse transferring/processing means amplifies and filters the optical pulses of the time correlation means to attenuate them. An output optical distributing means distributes the optical pulses of the optical pulse transferring/ processing means.

    Abstract translation: 公开了一种用于基于时间相关来控制光脉冲流周期的装置。 对反馈光脉冲和输入光脉冲进行时间交织，使它们不重叠在一起，然后对它们进行时间相关，从而大大降低了输入光脉冲流的偏振光束依赖性。 该装置包括用于产生时钟的时钟产生装置和用于从时钟产生装置接收时钟以产生与时钟发生装置的脉冲同步的光脉冲的光脉冲发生装置。 输入光脉冲分配装置分配输出光脉冲分配装置的反馈光脉冲，并分配光脉冲发生装置的光脉冲。 时间相关装置使输入光脉冲分配装置的光脉冲的时间相关，并且光脉冲传送/处理装置对时间相关装置的光脉冲进行放大和滤波以对其进行衰减。 输出光分配装置分配光脉冲传送/处理装置的光脉冲。

    RETAINER AND WAFER CARRIER INCLUDING THE SAME
    4.
    发明申请
    RETAINER AND WAFER CARRIER INCLUDING THE SAME 审中-公开
    保持架和滚动架，包括它们

    公开(公告)号：US20160082569A1

    公开(公告)日：2016-03-24

    申请号：US14729030

    申请日：2015-06-02

    Applicant: Sang-Hyun BAE ,  Kyu-Dong JUNG ,  Il-Hwan KIM ,  Jung-Hwan KIM ,  Hyuek-Jae LEE ,  Tae-Je CHO

    Inventor： Sang-Hyun BAE ,  Kyu-Dong JUNG ,  Il-Hwan KIM ,  Jung-Hwan KIM ,  Hyuek-Jae LEE ,  Tae-Je CHO

    IPC: B24B37/32

    CPC classification number: B24B37/32

    Abstract: A retainer for a wafer carrier comprising: a body including a plurality of slots configured to receive side surfaces of wafers; and for each of the slots, a supporting structure formed on a sidewall of the slot and configured to make contact with the side surfaces of a corresponding wafer, the supporting structure being spaced apart from an upper corner of the side surface of the corresponding wafer.

    Abstract translation: 一种用于晶片载体的保持器，包括：主体，其包括被配置为接收晶片的侧表面的多个槽; 并且对于每个狭槽，形成在所述槽的侧壁上并被配置为与相应晶片的侧表面接触的支撑结构，所述支撑结构与相应晶片的侧表面的上角隔开。

    Methods of packaging semiconductor devices including bridge patterns
    6.
    发明授权
    Methods of packaging semiconductor devices including bridge patterns 失效
    包括桥模式的半导体器件的封装方法

    公开(公告)号：US08304288B2

    公开(公告)日：2012-11-06

    申请号：US13155647

    申请日：2011-06-08

    Applicant: Hyuek-Jae Lee ,  Ji-Sun Hong ,  Tae-Je Cho ,  Jong-Yun Myung ,  Young-Bok Kim ,  Hyung-Sun Jang ,  Eun-Mi Kim

    Inventor： Hyuek-Jae Lee ,  Ji-Sun Hong ,  Tae-Je Cho ,  Jong-Yun Myung ,  Young-Bok Kim ,  Hyung-Sun Jang ,  Eun-Mi Kim

    IPC: H01L21/00

    CPC classification number: H01L21/76898 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2224/13

    Abstract: A method of packaging a semiconductor device may include providing a semiconductor substrate including first and second spaced apart semiconductor chip areas, and adhering a cover on the first and second spaced apart semiconductor chip areas of the semiconductor substrate. A scribe line may be formed through the semiconductor substrate between the first and second semiconductor chip areas with a semiconductor bridge pattern remaining connected between the first and second spaced apart semiconductor chip areas after forming the scribe line. The cover and the semiconductor bridge pattern may then be cut after forming the scribe line.

    Abstract translation: 封装半导体器件的方法可以包括提供包括第一和第二间隔开的半导体芯片区域的半导体衬底，以及将覆盖物粘附在半导体衬底的第一和第二间隔的半导体芯片区域上。 可以在第一和第二半导体芯片区域之间通过半导体衬底形成划线，在形成划线之后，半导体电桥图案保持连接在第一和第二间隔开的半导体芯片区域之间。 然后可以在形成划线之后切割盖和半导体桥模式。

    Methods of Packaging Semiconductor Devices Including Bridge Patterns
    8.
    发明申请
    Methods of Packaging Semiconductor Devices Including Bridge Patterns 失效
    包括桥模式的半导体器件的封装方法

    公开(公告)号：US20110306167A1

    公开(公告)日：2011-12-15

    申请号：US13155647

    申请日：2011-06-08

    Applicant: Hyuek-Jae Lee ,  Ji-Sun Hong ,  Tae-je Cho ,  Jong-Yun Myung ,  Young-Bok Kim ,  Hyung-Sun Jang ,  Eun-Mi Kim

    Inventor： Hyuek-Jae Lee ,  Ji-Sun Hong ,  Tae-je Cho ,  Jong-Yun Myung ,  Young-Bok Kim ,  Hyung-Sun Jang ,  Eun-Mi Kim

    IPC: H01L21/782

    CPC classification number: H01L21/76898 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2224/13

    Abstract: A method of packaging a semiconductor device may include providing a semiconductor substrate including first and second spaced apart semiconductor chip areas, and adhering a cover on the first and second spaced apart semiconductor chip areas of the semiconductor substrate. A scribe line may be formed through the semiconductor substrate between the first and second semiconductor chip areas with a semiconductor bridge pattern remaining connected between the first and second spaced apart semiconductor chip areas after forming the scribe line. The cover and the semiconductor bridge pattern may then be cut after forming the scribe line.

    Abstract translation: 封装半导体器件的方法可以包括提供包括第一和第二间隔开的半导体芯片区域的半导体衬底，以及将覆盖物粘附在半导体衬底的第一和第二间隔的半导体芯片区域上。 可以在第一和第二半导体芯片区域之间通过半导体衬底形成划线，在形成划线之后，半导体电桥图案保持连接在第一和第二间隔开的半导体芯片区域之间。 然后可以在形成划线之后切割盖和半导体桥模式。

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