公开(公告)号：US20050122149A1

公开(公告)日：2005-06-09

申请号：US11005821

申请日：2004-12-07

Applicant: Geun-Hee Cho ,  Kyu-Hyoun Kim

Inventor： Geun-Hee Cho ,  Kyu-Hyoun Kim

IPC: G11C8/00 ,  H03K5/04 ,  H03K5/135 ,  H03K5/151 ,  H03K5/156 ,  H03L7/081

CPC classification number: H03K5/151 ,  H03K5/135 ,  H03K5/1565 ,  H03L7/0812

Abstract: Delay-locked loop integrated circuits include a duty cycle correction circuit. This duty cycle correction circuit generates at least one output clock signal having a substantially uniform duty cycle in response to at least one input clock signal having a non-uniform duty cycle. The duty cycle correction circuit is also responsive to a standby control signal that synchronizes timing of power-saving duty cycle update operations within the duty cycle correction circuit. These update operations reset the set point of the correction circuit.

Abstract translation: 延迟锁定环集成电路包括占空比校正电路。 该占空比校正电路响应于具有不均匀占空比的至少一个输入时钟信号而产生具有基本均匀的占空比的至少一个输出时钟信号。 占空比校正电路还响应于在占空比校正电路内同步省电占空比更新操作的定时的待机控制信号。 这些更新操作重置校正电路的设定点。

公开(公告)号：US06236619B1

公开(公告)日：2001-05-22

申请号：US09559265

申请日：2000-04-27

Applicant: Geun-hee Cho ,  Chi-wook Kim

Inventor： Geun-hee Cho ,  Chi-wook Kim

IPC: G11C800

CPC classification number: G11C7/1072 ,  G11C7/22

Abstract: A synchronous dynamic random access memory (SDRAM) semiconductor device is provided. The SDRAM has a write-interrupt-write function and includes a first memory block for storing data, a first sense amplifier for sensing the data stored in the first memory block, first and second groups of input/output lines, connected to the first sense amplifier, and a write-interrupt-write signal generating portion for receiving an externally input write signal and an internal clock signal to generate a write-interrupt-write signal, and for providing the write-interrupt-write signal to the first sense amplifier. When an externally input data is written to the first memory block through the first group of input/output lines in response to the write signal enabled at a first point in time and the write signal is enabled at a second point in time to write data to the first memory block through the second group of input/output lines, the write-interrupt write signal generator enables the write-interrupt-write signal after a predetermined number of cycles of the internal clock signal from the second point in time at which the write signal is enabled, thereby immediately precharging the first group of input/output lines. As a result of this design, the write-interrupt-write function can be accurately carried out.

Abstract translation: 提供了一种同步动态随机存取存储器（SDRAM）半导体器件。 SDRAM具有写入中断写入功能，并且包括用于存储数据的第一存储器块，用于感测存储在第一存储器块中的数据的第一读出放大器，连接到第一感测的第一和第二组输入/输出线 放大器以及用于接收外部输入写入信号和内部时钟信号的写入中断写入信号产生部分，以产生写入中断写入信号，并向第一读出放大器提供写入中断写入信号。 当通过第一组输入/输出线将外部输入数据写入到第一存储块时，响应于在第一时间点使能写入信号，并且写入信号在第二时间点被使能以将数据写入 通过第二组输入/输出线的第一存储块，写中断写信号发生器在来自第二时间点的预定数量的内部时钟信号的周期之后启用写中断写信号， 信号被使能，从而立即对第一组输入/输出线进行预充电。 作为这种设计的结果，可以准确地执行写入中断写入功能。

公开(公告)号：US08824221B2

公开(公告)日：2014-09-02

申请号：US13616398

申请日：2012-09-14

Applicant: Geun-Hee Cho ,  Duc Nguyen ,  Dong-Hwi Kim

Inventor： Geun-Hee Cho ,  Duc Nguyen ,  Dong-Hwi Kim

IPC: G11C7/00 ,  G11C11/00 ,  G11C5/04 ,  G11C7/10 ,  G11C14/00

CPC classification number: G11C5/04 ,  G06F12/0638 ,  G11C7/10 ,  G11C7/1045 ,  G11C11/005 ,  G11C14/0018 ,  Y02D10/13

Abstract: A hybrid memory device is provided. The hybrid memory device includes a DRAM, a non-volatile memory and a control circuit. The control circuit selects one of output data of the DRAM and output data of the non-volatile memory according to a mode selecting signal and output the selected data. The control circuit outputs data requested to be output from the DRAM when the data requested to be output is in the DRAM, and may output the data requested to be output from the non-volatile memory when the data requested to be output is in the non-volatile memory. Accordingly, the hybrid memory device has a high speed in a read and write operation, and has low power consumption.

Abstract translation: 提供了一种混合存储器件。 混合存储器件包括DRAM，非易失性存储器和控制电路。 控制电路根据模式选择信号选择DRAM的输出数据和非易失性存储器的输出数据之一，并输出所选择的数据。 当请求输出的数据在DRAM中时，控制电路输出请求从DRAM输出的数据，并且当请求输出的数据为非数据时，可以输出请求从非易失性存储器输出的数据 非易失存储器 因此，混合存储装置在读取和写入操作中具有高速度，并且具有低功耗。

公开(公告)号：US07375564B2

公开(公告)日：2008-05-20

申请号：US10716146

申请日：2003-11-18

Applicant: Geun-Hee Cho ,  Byung-Hoon Jeong ,  Kyu-Hyoun Kim

Inventor： Geun-Hee Cho ,  Byung-Hoon Jeong ,  Kyu-Hyoun Kim

IPC: H03L7/06

CPC classification number: H03L7/0814 ,  H03K5/135 ,  H03K2005/00208 ,  H03L7/0818

Abstract: A delay-locked loop includes a phase detector, a delay line, and a filter unit. The phase detector compares the phase of the external clock signal with that of the feedback clock signal and outputs a phase difference as an error control signal. The delay line includes delay cells having various unit time delays. The number of delay cells is adjusted in response to a shift signal. The delay line receives the external clock signal and outputs an output clock signal. The filter unit generates the shift signal in response to the error control signal. In the delay-locked loop, the front delay cells, which compensate for a delay of an external clock signal having a high frequency, have short unit time delays. The rear delay cells, which compensate for a delay of the external clock signal having a low frequency, have long unit time delays.

Abstract translation: 延迟锁定环包括相位检测器，延迟线和滤波器单元。 相位检测器将外部时钟信号的相位与反馈时钟信号的相位进行比较，并输出相位差作为误差控制信号。 延迟线包括具有各种单位时间延迟的延迟单元。 响应于移位信号调整延迟单元的数量。 延迟线接收外部时钟信号并输出​​输出时钟信号。 滤波器单元响应于误差控制信号产生移位信号。 在延迟锁定环路中，补偿具有高频率的外部时钟信号的延迟的前延迟单元具有较短的单位时间延迟。 补偿具有低频率的外部时钟信号的延迟的后延迟单元具有长的单位时间延迟。

公开(公告)号：US07199634B2

公开(公告)日：2007-04-03

申请号：US11005821

申请日：2004-12-07

Applicant: Geun-Hee Cho ,  Kyu-Hyoun Kim

Inventor： Geun-Hee Cho ,  Kyu-Hyoun Kim

IPC: H03K3/017

CPC classification number: H03K5/151 ,  H03K5/135 ,  H03K5/1565 ,  H03L7/0812

Abstract: Delay-locked loop integrated circuits include a duty cycle correction circuit. This duty cycle correction circuit generates at least one output clock signal having a substantially uniform duty cycle in response to at least one input clock signal having a non-uniform duty cycle. The duty cycle correction circuit is also responsive to a standby control signal that synchronizes timing of power-saving duty cycle update operations within the duty cycle correction circuit. These update operations reset the set point of the correction circuit.

Abstract translation: 延迟锁定环集成电路包括占空比校正电路。 该占空比校正电路响应于具有不均匀占空比的至少一个输入时钟信号而产生具有基本均匀的占空比的至少一个输出时钟信号。 占空比校正电路还响应于在占空比校正电路内同步省电占空比更新操作的定时的待机控制信号。 这些更新操作重置校正电路的设定点。

公开(公告)号：US20130077382A1

公开(公告)日：2013-03-28

申请号：US13616398

申请日：2012-09-14

Applicant: Geun-Hee CHO ,  Duc NGUYEN ,  Dong-Hwi KIM

Inventor： Geun-Hee CHO ,  Duc NGUYEN ,  Dong-Hwi KIM

IPC: G11C11/21 ,  G11C16/04 ,  G06F12/02 ,  G11C7/10

CPC classification number: G11C5/04 ,  G06F12/0638 ,  G11C7/10 ,  G11C7/1045 ,  G11C11/005 ,  G11C14/0018 ,  Y02D10/13

Abstract: A hybrid memory device is provided. The hybrid memory device includes a DRAM, a non-volatile memory and a control circuit. The control circuit selects one of output data of the DRAM and output data of the non-volatile memory according to a mode selecting signal and output the selected data. The control circuit outputs data requested to be output from the DRAM when the data requested to be output is in the DRAM, and may output the data requested to be output from the non-volatile memory when the data requested to be output is in the non-volatile memory. Accordingly, the hybrid memory device has a high speed in a read and write operation, and has low power consumption.

Abstract translation: 提供了一种混合存储器件。 混合存储器件包括DRAM，非易失性存储器和控制电路。 控制电路根据模式选择信号选择DRAM的输出数据和非易失性存储器的输出数据之一，并输出所选择的数据。 当请求输出的数据在DRAM中时，控制电路输出请求从DRAM输出的数据，并且当请求输出的数据为非数据时，可以输出请求从非易失性存储器输出的数据 非易失存储器 因此，混合存储装置在读取和写入操作中具有高速度，并且具有低功耗。

公开(公告)号：US20120300569A1

公开(公告)日：2012-11-29

申请号：US13477300

申请日：2012-05-22

Applicant: Geun Hee Cho

Inventor： Geun Hee Cho

IPC: G11C7/00

CPC classification number: G11C11/401 ,  G06F13/1636 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40615 ,  Y02D10/14

Abstract: A memory system and a refresh control method thereof are provided. The memory system includes a semiconductor memory device including a plurality of memory cells and a memory controller configured to generate a special command for searching for refresh information stored in the semiconductor memory device and to control a refresh operation of the semiconductor memory device. The semiconductor memory device is configured to output the refresh information to the memory controller in response to the special command generated by the memory controller.

Abstract translation: 提供了一种存储器系统及其刷新控制方法。 存储器系统包括包括多个存储器单元的半导体存储器件和被配置为产生用于搜索存储在半导体存储器件中的刷新信息的特殊命令并且控制半导体存储器件的刷新操作的存储器控​​制器。 半导体存储器件被配置为响应于存储器控制器产生的特殊命令将刷新信息输出到存储器控制器。

公开(公告)号：US07236012B2

公开(公告)日：2007-06-26

申请号：US10970016

申请日：2004-10-22

Applicant: Geun-hee Cho ,  Jung-bae Lee

Inventor： Geun-hee Cho ,  Jung-bae Lee

IPC: H03K19/0175

CPC classification number: G11C7/1051 ,  G11C7/1057

Abstract: A data output driver of a semiconductor memory device can minimize a difference in slew rate of an output signal according to a selected bit organization. The data output driver includes a pull-up driver and a pull-down driver. The pull-up driver pulls up an output terminal and the pull-down driver pulls down the output terminal. In particular, current driving capabilities of the pull-up driver and/or the pull-down driver are changed in response to bit organization information signals of the semiconductor memory device.

Abstract translation: 半导体存储器件的数据输出驱动器可以根据所选位组织来最小化输出信号的转换速率差。 数据输出驱动器包括一个上拉驱动器和一个下拉驱动器。 上拉驱动器拉出输出端子，下拉驱动器拉出输出端子。 特别地，上拉驱动器和/或下拉驱动器的当前驱动能力响应于半导体存储器件的位组织信息信号而改变。

公开(公告)号：US08750068B2

公开(公告)日：2014-06-10

申请号：US13477300

申请日：2012-05-22

Applicant: Geun Hee Cho

Inventor： Geun Hee Cho

IPC: G11C7/00 ,  G11C11/401 ,  G11C11/406

CPC classification number: G11C11/401 ,  G06F13/1636 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40615 ,  Y02D10/14

Abstract: A memory system and a refresh control method thereof are provided. The memory system includes a semiconductor memory device including a plurality of memory cells and a memory controller configured to generate a special command for searching for refresh information stored in the semiconductor memory device and to control a refresh operation of the semiconductor memory device. The semiconductor memory device is configured to output the refresh information to the memory controller in response to the special command generated by the memory controller.

Abstract translation: 提供了一种存储器系统及其刷新控制方法。 存储器系统包括包括多个存储器单元的半导体存储器件和被配置为产生用于搜索存储在半导体存储器件中的刷新信息的特殊命令并且控制半导体存储器件的刷新操作的存储器控​​制器。 半导体存储器件被配置为响应于存储器控制器产生的特殊命令将刷新信息输出到存储器控制器。

公开(公告)号：US20080211554A1

公开(公告)日：2008-09-04

申请号：US12104997

申请日：2008-04-17

Applicant: Geun Hee Cho ,  Byung-Hoon Jeong ,  Kyu-Hyoun Kim

Inventor： Geun Hee Cho ,  Byung-Hoon Jeong ,  Kyu-Hyoun Kim

IPC: H03L7/06 ,  H03H11/26

CPC classification number: H03L7/0814 ,  H03K5/135 ,  H03K2005/00208 ,  H03L7/0818

Abstract: A time delay compensation circuit comprises delay cells having various unit time delays. A delay-locked loop, a type of the time delay compensation circuit, includes a phase detector, a delay line, and a filter unit. The phase detector compares the phase of the external clock signal with that of the feedback clock signal and outputs a phase difference as an error control signal. The delay line includes a plurality of delay cells having various unit time delays. The number of delay cells is adjusted in response to a predetermined shift signal. The delay line receives the external clock signal and outputs an output clock signal, which is obtained by controlling the phase of the external clock signal. The filter unit generates the shift signal, which selects the number of delay cells in the delay line, in response to the error control signal. In the time delay compensation circuit, the front delay cells, which are used to compensate for a delay of an external clock signal having a high frequency, have short unit time delays so as to reduce jitter due to quantization error. Also, the rear delay cells, which are used to compensate for a delay of the external clock signal having a low frequency, have long unit time delays so as to reduce the number of delay cells required for the delay compensation.

Abstract translation: 时间延迟补偿电路包括具有各种单位时间延迟的延迟单元。 延迟锁定环路，延时补偿电路的一种类型，包括相位检测器，延迟线和滤波器单元。 相位检测器将外部时钟信号的相位与反馈时钟信号的相位进行比较，并输出相位差作为误差控制信号。 延迟线包括具有各种单位时间延迟的多个延迟单元。 响应于预定的移位信号来调整延迟单元的数量。 延迟线接收外部时钟信号并输出​​通过控制外部时钟信号的相位而获得的输出时钟信号。 滤波器单元响应于误差控制信号产生移位信号，该移位信号选择延迟线中的延迟单元的数量。 在延时补偿电路中，用于补偿具有高频率的外部时钟信号的延迟的前延迟单元具有短的单位时间延迟，以便减少由于量化误差引起的抖动。 此外，用于补偿具有低频率的外部时钟信号的延迟的后延迟单元具有长的单位时间延迟，以便减少延迟补偿所需的延迟单元的数量。