公开(公告)号：US20080020566A1

公开(公告)日：2008-01-24

申请号：US11902976

申请日：2007-09-27

Applicant: Frank Egitto ,  How Lin

Inventor： Frank Egitto ,  How Lin

IPC: H01L21/44

CPC classification number: H05K3/4007 ,  G01R1/06711 ,  G01R1/0735 ,  H05K1/0393 ,  H05K3/365 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09627 ,  H05K2201/09745 ,  H05K2201/10378

Abstract: A method of making an interposer in which at least two dielectric layers are bonded to each other to sandwich a plurality of conductors there-between. The conductors each electrically couple a respective pair of opposed electrical contacts which are formed within and protrude from openings which are also formed within the dielectric layers as part of this method. The resulting interposer is ideally suited for use as part of a test apparatus to interconnect highly dense patterns of solder ball contacts of a semiconductor chip to lesser dense arrays of contacts on the apparatus's printed circuit board.

Abstract translation: 一种制造其中至少两个电介质层彼此结合以夹在其间的多个导体的插入件的方法。 这些导体各自电耦合相应的一对相对的电触点，其形成在也作为该方法的一部分的电介质层内形成的开口内并从其中突出。 所得到的内插器非常适合用作测试装置的一部分，以将半导体芯片的高密度图案的焊球接触件与装置的印刷电路板上的较小致密的触点阵列相互连接。

公开(公告)号：US20070006452A1

公开(公告)日：2007-01-11

申请号：US11177413

申请日：2005-07-11

Applicant: Frank Egitto ,  Voya Markovich ,  Luis Matienzo

Inventor： Frank Egitto ,  Voya Markovich ,  Luis Matienzo

IPC: B32B37/00 ,  H05K3/30

CPC classification number: H05K3/462 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H05K3/4069 ,  H05K3/429 ,  H05K3/445 ,  H05K2201/015 ,  H05K2201/0245 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/1152 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49163 ,  Y10T29/49165 ,  Y10T156/1056 ,  Y10T156/1062

Abstract: A method of making a circuitized substrate which includes a high temperature dielectric material in combination with a low temperature conductive paste, the paste including an organic binder component and at least one metallic component. The flakes of the metallic component are sintered to form a conductive path through the dielectric when the dielectric is used as a layer in the substrate.

Abstract translation: 一种制造电路化基板的方法，该基板包括与低温导电浆料组合的高温电介质材料，所述糊料包括有机粘合剂成分和至少一种金属成分。 当电介质用作衬底中的层时，金属部件的薄片被烧结以形成通过电介质的导电路径。

公开(公告)号：US20060022310A1

公开(公告)日：2006-02-02

申请号：US10900386

申请日：2004-07-28

Applicant: Frank Egitto ,  John Lauffer ,  How Lin ,  Voya Markovich ,  David Thomas

Inventor： Frank Egitto ,  John Lauffer ,  How Lin ,  Voya Markovich ,  David Thomas

IPC: H01L23/58

CPC classification number: G11C5/06 ,  B82Y10/00 ,  G02B6/43 ,  H01L23/48 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/16 ,  H05K1/181 ,  H05K3/429 ,  H05K3/4611 ,  H05K2201/0166 ,  H05K2201/0179 ,  H05K2201/09763 ,  H05K2201/10159 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: An electrical assembly which includes a circuitized substrate comprised of an organic dielectric material having a first electrically conductive pattern thereon. At least part of the dielectric layer and pattern form the first, base portion of an organic memory device, the remaining portion being a second, polymer layer formed over the part of the pattern and a second conductive circuit formed on the polymer layer. A second dielectric layer if formed over the second conductive circuit and first circuit pattern to enclose the organic memory device. The device is electrically coupled to a first electrical component through the second dielectric layer and this first electrical component is electrically coupled to a second electrical component. A method of making the electrical assembly is also provided, as is an information handling system adapted for using one or more such electrical assemblies as part thereof.

Abstract translation: 一种电气组件，其包括由其上具有第一导电图案的有机电介质材料构成的电路化衬底。 电介质层和图案的至少一部分形成有机存储器件的第一基底部分，其余部分是形成在图案部分上的第二聚合物层和形成在聚合物层上的第二导电电路。 如果形成在第二导电电路上的第二电介质层和第一电路图案以包围有机存储器件。 该器件通过第二介电层电耦合到第一电气部件，并且该第一电气部件电耦合到第二电气部件。 还提供了制造电气组件的方法，以及适于使用一个或多个这样的电气组件作为其一部分的信息处理系统。

公开(公告)号：US08198739B2

公开(公告)日：2012-06-12

申请号：US12836612

申请日：2010-08-13

Applicant: How Lin ,  Frank Egitto ,  Voya Markovich

Inventor： How Lin ,  Frank Egitto ,  Voya Markovich

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L23/3157 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/72 ,  H01L2224/0226 ,  H01L2224/02335 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73251 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/81901 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/16 ,  H01L2224/72

Abstract: A method of forming a compressible contact structure on a semi-conductor chip which comprises bonding a compressible polymer layer to the chip's surface, forming a plurality of openings within the layer, depositing electrically conductive material within the openings to form electrical connections with the chip's contacts, forming a plurality of electrically conductive line elements on the polymer layer extending from a respective opening and each including an end portion, and forming a plurality of contact members each on a respective one of the line segment end portions. The compressible polymer layer allows the contact members to deflect toward (compress) the chip when the contact members are engaged by an external force or forces. A semi-conductor chip including such a compressible contact structure is also provided.

Abstract translation: 一种在半导体芯片上形成可压缩接触结构的方法，包括将可压缩的聚合物层粘合到芯片的表面，在该层内形成多个开口，在开口内沉积导电材料以形成与芯片的触点的电连接 在聚合物层上形成多个导电线元件，所述多个导电线元件从相应的开口延伸并且各自包括端部，并且在所述线段端部中的相应一个上形成多个接触元件。 当可接触构件通过外力或力接合时，可压缩聚合物层允许接触构件偏转（压缩）芯片。 还提供了包括这种可压缩接触结构的半导体芯片。

公开(公告)号：US20060214010A1

公开(公告)日：2006-09-28

申请号：US11401401

申请日：2006-04-11

Applicant: Benson Chan ,  Frank Egitto ,  Roy Magnuson ,  Voya Markovich ,  David Thomas

Inventor： Benson Chan ,  Frank Egitto ,  Roy Magnuson ,  Voya Markovich ,  David Thomas

IPC: G06K19/06

CPC classification number: G06K7/084 ,  G06K17/00 ,  G06K19/005 ,  G06K19/07354 ,  G06K2017/0064 ,  H05K1/0221 ,  H05K1/0222 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09809 ,  H05K2203/0733 ,  Y10T29/49165

Abstract: A circuitized substrate in which selected ones of the signal conductors are substantially surrounded by shielding members which shield the conductors during passage of high frequency signals, e.g., to reduce noise. The shielding members may form solid members which lie parallel and/or perpendicular to the signal conductors, and may also be substantially cylindrical in shape to surround a conductive thru-hole which also forms part of the substrate. An electrical assembly and an information handling system are also defined.

Abstract translation: 电路化基板，其中所选择的信号导体基本上由在高频信号通过期间屏蔽导体的屏蔽构件包围，例如降低噪声。 屏蔽构件可以形成平行和/或垂直于信号导体的固体构件，并且也可以基本上为圆柱形，以包围也形成衬底的一部分的导电通孔。 还定义了电组件和信息处理系统。

公开(公告)号：US20050008833A1

公开(公告)日：2005-01-13

申请号：US10854598

申请日：2004-05-26

Applicant: Brian Curcio ,  Frank Egitto ,  Robert Japp ,  Thomas Miller ,  Manh-Quan Nguyen ,  Douglas Powell

Inventor： Brian Curcio ,  Frank Egitto ,  Robert Japp ,  Thomas Miller ,  Manh-Quan Nguyen ,  Douglas Powell

IPC: H01L21/48 ,  H05K3/40 ,  H05K3/46 ,  B32B3/00

CPC classification number: H01L21/486 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/462 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/0191 ,  H05K2203/0264 ,  H05K2203/061 ,  H05K2203/1152 ,  Y10S438/976 ,  Y10T29/49165 ,  Y10T428/24917 ,  Y10T428/28 ,  Y10T428/2804 ,  Y10T428/2839 ,  Y10T428/2848

Abstract: A method for producing small pitch z-axis electrical interconnections in layers of dielectric materials which are applied to printed wiring boards and diverse electronic packages. A method for parallel fabrication of intermediate structures which are subsequently jointed to form a final structure. In addition there is provided a z-interconnected electrical structure, employing dielectric materials such as resin coated copper, employable in the manufacture of diverse type of electronic packages, including printed wiring boards (PWBs), substrates, multi-chip modules and the like.

公开(公告)号：US20080105457A1

公开(公告)日：2008-05-08

申请号：US12007178

申请日：2008-01-08

Applicant: Frank Egitto ,  Voya Markovich ,  Luis Matienzo

Inventor： Frank Egitto ,  Voya Markovich ,  Luis Matienzo

IPC: H05K1/03

CPC classification number: H05K3/462 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H05K3/4069 ,  H05K3/429 ,  H05K3/445 ,  H05K2201/015 ,  H05K2201/0245 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/1152 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49163 ,  Y10T29/49165 ,  Y10T156/1056 ,  Y10T156/1062

Abstract: A circuitized substrate which includes a high temperature dielectric material in combination with a low temperature conductive paste, the paste including an organic binder component and at least one metallic component. The flakes of the metallic component are sintered to form a conductive path through the dielectric when the dielectric is used as a layer in the substrate.

Abstract translation: 一种电路化基板，包括与低温导电浆料组合的高温电介质材料，所述糊料包括有机粘合剂成分和至少一种金属成分。 当电介质用作衬底中的层时，金属部件的薄片被烧结以形成通过电介质的导电路径。

公开(公告)号：US20080054476A1

公开(公告)日：2008-03-06

申请号：US11976629

申请日：2007-10-26

Applicant: Frank Egitto ,  Stephen Krasniak ,  John Lauffer ,  Voya Markovich ,  Luis Matienzo

Inventor： Frank Egitto ,  Stephen Krasniak ,  John Lauffer ,  Voya Markovich ,  Luis Matienzo

IPC: H01L23/52

CPC classification number: H05K3/384 ,  H05K1/056 ,  H05K3/386 ,  H05K2201/0355 ,  H05K2201/0358 ,  H05K2203/0353 ,  H05K2203/0723

Abstract: A circuitized substrate with a conductive layer which assures enhanced adhesion of the layer to selected dielectric layers used to form the circuitized substrate. The conductive layer includes at least one surface with the appropriate roughness to enable such adhesion and also good signal passage if the layer is used as a signal layer.

Abstract translation: 具有导电层的电路化衬底，其确保该层对用于形成电路化衬底的所选介电层的附着力增强。 导电层包括具有适当粗糙度的至少一个表面以实现这种粘附，并且如果该层用作信号层，则还具有良好的信号通过。

公开(公告)号：US20070075726A1

公开(公告)日：2007-04-05

申请号：US11607973

申请日：2006-12-04

Applicant: Benson Chan ,  Frank Egitto ,  Voya Markovich

Inventor： Benson Chan ,  Frank Egitto ,  Voya Markovich

IPC: G01R31/26

CPC classification number: G01R1/06711 ,  G01R1/0735 ,  G01R1/07378 ,  H05K1/0393 ,  H05K3/365 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09627 ,  H05K2201/09745 ,  H05K2201/10378

Abstract: A test apparatus which uses a pair of substrates and housing to interconnect a host substrate (e.g., PCB) to an electronic device (e.g., semiconductor chip) to accomplish testing of the device. The apparatus includes a housing designed for being positioned on the PCB and have one of the substrates oriented therein during device engagement. The engaging contacts of the upper (second) substrate are sculpted to assure effective chip connection.

Abstract translation: 一种测试装置，其使用一对基板和壳体将主机基板（例如，PCB）与电子设备（例如，半导体芯片）互连以完成设备的测试。 该装置包括被设计用于定位在PCB上的壳体，并且在装置接合期间其中一个基板定向于其中。 上（第二）衬底的接合触点被雕刻以确保有效的芯片连接。

公开(公告)号：US20060289607A1

公开(公告)日：2006-12-28

申请号：US11168182

申请日：2005-06-28

Applicant: Stephen Buchwalter ,  David Danovitch ,  Frank Egitto ,  Peter Gruber ,  Eric Perfecto ,  Da-Yuan Shih

Inventor： Stephen Buchwalter ,  David Danovitch ,  Frank Egitto ,  Peter Gruber ,  Eric Perfecto ,  Da-Yuan Shih

IPC: B23K35/12

CPC classification number: B23K35/3613

Abstract: A method for constructing a composite solder transfer moldplate for flip chip wafer bumping of a substrate, comprising the steps of coating at least one polymer layer onto a first side of a transparent plate, the plate having a thermal expansion coefficient similar to that of the substrate; and forming a multiplicity of cavities in a polymer layer on one side of the plate, each cavity being for receiving solder. A moldplate made by the method. The structure has required behavior through temperature excursions between room temperature and various solder molten temperatures.

Abstract translation: 一种用于构造用于衬底的倒装芯片晶片凸起的复合焊料传递模板的方法，包括以下步骤：将至少一个聚合物层涂覆到透明板的第一侧上，该板具有与衬底的热膨胀系数相似的热膨胀系数 ; 并且在该板的一侧上的聚合物层中形成多个空腔，每个空腔用于接收焊料。 通过该方法制成的模板。 该结构通过室温和各种焊料熔融温度之间的温度偏移需要行为。