公开(公告)号：US3898482A

公开(公告)日：1975-08-05

申请号：US45632674

申请日：1974-03-29

Applicant: FAIRCHILD CAMERA INSTR CO

Inventor： HOLT JR JAMES G

IPC: H04B1/10 ,  H01L27/07 ,  H01L27/082 ,  H03K5/08

CPC classification number: H01L27/0826 ,  H01L27/0755

Abstract: An improved noise suppression circuit which includes a first transistor having a collector, an emitter coupled to the input of the circuit, and a base coupled to an output of the circuit through an impedance means. The circuit includes a second transistor having a base coupled to the collector of the first transistor, a collector coupled to a reference potential, and an emitter integral with the impedance means. The circuit of the present invention can be constructed to suppress positive-going noise pulses, negative-going noise pulses, or one of each can be cascaded to suppress both positive and negative-going noise pulses.

Abstract translation: 一种改进的噪声抑制电路，其包括具有集电极的第一晶体管，耦合到所述电路的输入的发射极，以及通过阻抗装置耦合到所述电路的输出的基极。 电路包括第二晶体管，其具有耦合到第一晶体管的集电极的基极，耦合到参考电位的集电极和与阻抗装置集成的发射极。 本发明的电路可以被构造成抑制正向噪声脉冲，负向噪声脉冲，或者可以级联其中的一个以抑制正和负噪声脉冲。

公开(公告)号：US3891977A

公开(公告)日：1975-06-24

申请号：US48838774

申请日：1974-07-15

Applicant: FAIRCHILD CAMERA INSTR CO

Inventor： AMELIO GILBERT F ,  LIVEZEY JACK A ,  SALSBURY PHILLIP J

IPC: G11C27/04 ,  G11C19/28 ,  G11C11/40

CPC classification number: G11C19/287 ,  G11C19/285

Abstract: A charge coupled memory device is disclosed which comprises a plurality of CCD shift registers, input write circuitry, output read circuitry, and a plurality of charge comparison circuits, each of which are coupled between corresponding ones of the CCD shift registers. Each charge comparison circuit includes an active charge comparator device having a pair of field effect transistors that are cross-coupled to one another. Charge is applied from the output of the preceding shift register to an input of the charge comparison circuit, and the charge is compared with a reference charge developed from a reference signal. The charge comparison circuit provides complementary logic output signals that correspond to whether the input charge is greater or less than the reference charge. The charge comparison circuit is insensitive to voltage variations in the DC power supply and does not consume any DC power. The output logic signals are compatible with the logic levels of the external circuitry.

Abstract translation: 公开了一种电荷耦合存储器件，其包括多个CCD移位寄存器，输入写入电路，输出读取电路和多个电荷比较电路，每个电荷比较电路耦合在相应的CCD移位寄存器之间。 每个电荷比较电路包括具有彼此交叉耦合的一对场效应晶体管的有源电荷比较器装置。 从前一移位寄存器的输出向充电比较电路的输入端施加充电，并将该电荷与从参考信号产生的参考电荷进行比较。 电荷比较电路提供对应于输入电荷是大于还是小于参考电荷的互补逻辑输出信号。 电荷比较电路对直流电源的电压变化不敏感，不消耗任何直流电力。 输出逻辑信号与外部电路的逻辑电平兼容。

公开(公告)号：US3848139A

公开(公告)日：1974-11-12

申请号：US39749473

申请日：1973-09-14

Applicant: FAIRCHILD CAMERA INSTR CO

Inventor： HOLT J

IPC: H03K3/2897 ,  H03K5/24 ,  H03K5/20

CPC classification number: H03K3/2897 ,  H03K5/2418

Abstract: A high-gain comparator circuit including a pair of input transistors, a constant current source, a pair of shunting transistors, and a pair of diodes geometrically scaled to corresponding ones of the shunting transistors, all of which are connected to provide a regenerative circuit which produces high slope bilevel output signals at the circuit switching point.

Abstract translation: 一种高增益比较器电路，包括一对输入晶体管，恒流源，一对分流晶体管和一对几何尺寸对应的分流晶体管的二极管，所有这些都被连接以提供再生电路， 在电路切换点产生高斜率双电平输出信号。

公开(公告)号：US3806772A

公开(公告)日：1974-04-23

申请号：US22404572

申请日：1972-02-07

Applicant: FAIRCHILD CAMERA INSTR CO

Inventor： EARLY J

IPC: H01L29/768 ,  H03F1/18 ,  H01L11/14

CPC classification number: H01L29/76816 ,  H03F1/18

Abstract: A charge coupled distributed amplifier comprises a first plurality of charge storage wells arranged along a first selected line, a second plurality of charge storage wells arranged along a second selected line, and a multiplicity of amplifier means, each amplifier means electrically coupling one charge storage well in the first plurality of wells to a corresponding charge storage well in the second plurality of wells. Charges are driven along the first and second pluralities of charge storage wells in synchronization. The same charge in the first plurality of charge storage wells creates an additional increment of charge in each charge storage well connected to the output of each amplifier means which adds in that well to the previously accumulated charge in the second plurality of charge storage wells. Thus a given amount of input charge is amplified coherently to produce a detectable output signal.

Abstract translation: 电荷耦合分布放大器包括沿着第一选定线布置的第一多个电荷存储阱，沿着第二选定线布置的第二多个电荷存储阱和多个放大器装置，每个放大器装置电耦合一个电荷存储阱 在第一组多个孔中，在第二个多个孔中与相应的电荷存储阱相对。 同步沿着第一和第二多个电荷存储阱驱动电荷。 在第一多个电荷存储阱中的相同电荷在每个电荷存储阱中产生附加的电荷增量，其连接到每个放大器装置的输出，该放大器装置将该阱中的第二个多个电荷存储阱中的先前累积的电荷相加。 因此，给定量的输入电荷被相干地放大以产生可检测的输出信号。

公开(公告)号：US3772660A

公开(公告)日：1973-11-13

申请号：US3772660D

申请日：1969-07-02

Applicant: FAIRCHILD CAMERA INSTR CO

Inventor： NORMAN R

IPC: G11C11/411 ,  H01L29/08 ,  H03K3/286 ,  H03K3/288 ,  H03K3/29 ,  G11C11/40 ,  G11C5/02

CPC classification number: H03K3/288 ,  G11C11/4116 ,  H01L29/0813 ,  H03K3/286 ,  H03K3/29

Abstract: A memory cell having two transistors, each transistor having two emitters, a base, and a collector; the bases and the collectors of the transistors are cross-coupled; by the application of a first signal to one of the emitters of each of the two transistors simultaneously, and a second signal at the same time to the other emitter of only one of the two transistors, the transistor having the second signal at its emitter is placed in a conducting state so that data is stored in the cell having the actuated emitter.

公开(公告)号：US3765590A

公开(公告)日：1973-10-16

申请号：US3765590D

申请日：1972-05-08

Applicant: FAIRCHILD CAMERA INSTR CO

Inventor： DUFFEK E ,  LANE J ,  LEHNER W ,  FUNK E ,  JANKOWSKI A ,  OLIVER F ,  SCHNEIDER M

IPC: H01L21/00 ,  H01L23/495 ,  B23K1/00

CPC classification number: H01L21/67144 ,  H01L23/49541 ,  H01L23/49551 ,  H01L2924/0002 ,  Y10T29/49121 ,  Y10T29/53183 ,  H01L2924/00

Abstract: Semiconductor devices containing integrated circuits are attached directly to external package leads by pressing simultaneously a plurality of groups of leads against bonding pads on a plurality of face-up semiconductor dice and heating the composite structures. Solder bumps on the bonding pads contain hard pedestals which prevent the overlying leads from being pushed into the faces of the semiconductor devices while the solder on the solder bumps melts to form the bonds between the leads and the underlying semiconductor dice. The process for carrying out this operation lowers significantly the cost of each packaged semiconductor device and the resulting structure is more reliable than structures of the prior art.

Abstract translation: 包含集成电路的半导体器件通过同时将多组引线抵抗多个面朝上半导体晶片上的接合焊盘并且加热复合结构而直接附接到外部封装引线。 接合焊盘上的焊料凸起包含硬的基座，其防止上覆的引线被推入半导体器件的表面，同时焊料凸块上的焊料熔化以形成引线和下面的半导体管芯之间的结合。 执行该操作的过程显着降低了每个封装的半导体器件的成本，并且所得到的结构比现有技术的结构更可靠。

公开(公告)号：US3752118A

公开(公告)日：1973-08-14

申请号：US3752118D

申请日：1971-10-13

Applicant: FAIRCHILD CAMERA INSTR CO

Inventor： SOLOMON R ,  DE FEVERE D

IPC: C30B19/06 ,  B05C3/09

CPC classification number: C30B19/062

Abstract: Apparatus and method for the deposition of semiconductor material onto semiconductor wafers by immersing them in a source of liquid semiconductor material. The apparatus includes a chamber, a wafer holder, and a plug, the plug adapted to rest upon the liquid residing in the chamber during mixing of the liquid, and to be pushed through the liquid, thereby forcing the liquid to flow through the space between the plug and the walls of the chamber, that space acting as a filter to prevent solid contaminants from coming into contact with the wafers in the holder. The floating plug also serves to prevent volatilization of constituents during the mixing of the semiconductor and dopants.

公开(公告)号：US3723258A

公开(公告)日：1973-03-27

申请号：US3723258D

申请日：1970-12-14

Applicant: FAIRCHILD CAMERA INSTR CO

Inventor： PODELL J ,  WHELTON R

IPC: C25D11/04 ,  H01L21/316 ,  H01L23/522 ,  C23B9/00 ,  C23B5/46 ,  C23B5/48

CPC classification number: H01L21/31687 ,  C25D11/022 ,  C25D11/04 ,  C25D11/08 ,  H01L23/522 ,  H01L2924/0002 ,  Y10S148/085 ,  Y10S148/118 ,  H01L2924/00

Abstract: MULTIPLE LAYERS OF CONDUCTIVE INTERCONNECTS ARE FORMED ON AN INTEGRATED CIRCUIT BY DEPOSTING LAYERS OF A METAL (TYPICALLY ALUMINUM) ON THE SURFACE OF THE CIRCUIT AND THEN SELECTIVELY ANODIZING THESE LAYERS TO FORM INSULATION LAYERS OR LAYERS OF CONDUCTIVE INTERCONNECTS. MASKING MATERIAL IS USED TO PREVENT THE ANODIZATION OF AND THUS TO DEFINE, THE CONDUCTIVE LEAD PATTERNS.

公开(公告)号：US3663820A

公开(公告)日：1972-05-16

申请号：US3663820D

申请日：1970-10-07

Applicant: FAIRCHILD CAMERA INSTR CO

Inventor： BURNS JOSEPH

IPC: H01J29/38 ,  H01J39/12

CPC classification number: H01J29/38

Abstract: A silicon wafer has a plurality of spaced diode junctions formed in its upper surface and through openings in a silicon dioxide layer. A conductive grid is disposed over the silicon dioxide layer and has openings exposing the elemental diode surfaces. The top of the exposed diode surfaces are cesiated. Each of the diodes is reverse biased and the cesiated surfaces of the diodes emit electrons, appropriately adjusting their potential in response to radiation applied to the adjacent rear surface of the wafer.

Abstract translation: 硅晶片在其上表面中形成有多个间隔开的二极管结，并且通过二氧化硅层中的开口。 导电栅格设置在二氧化硅层之上并且具有露出元件二极管表面的开口。 暴露的二极管表面的顶部被削弱。 每个二极管被反向偏置，并且二极管的开关表面发射电子，适当地调整其响应于施加到晶片的相邻后表面的辐射的电位。

公开(公告)号：US3650778A

公开(公告)日：1972-03-21

申请号：US3650778D

申请日：1969-10-29

Applicant: FAIRCHILD CAMERA INSTR CO

Inventor： DUMESNIL MAURICE E ,  HEWITT ROBERT R ,  BOZARTH JOSEPH L

IPC: C03C3/21 ,  C03C8/24 ,  C03C3/00

CPC classification number: C03C8/24 ,  C03C3/21

Abstract: Low-melting, low-expansion, lead-free glass compositions are provided for sealing ceramics parts and encapsulating ceramic substrates. In addition to having a thermal expansion matching that of alumina, the glass compositions provide for the formation of a glass-to-alumina seal in the 380* to 450* C. temperature range.

Abstract translation: 提供低熔点，低膨胀，无铅玻璃组合物用于密封陶瓷部件和封装陶瓷基板。 除了具有与氧化铝相匹配的热膨胀之外，玻璃组合物还可在380-450℃的温度范围内形成玻璃 - 氧化铝密封。