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    Methods for selective reverse mask planarization and interconnect structures formed thereby
    2.
    发明授权
    Methods for selective reverse mask planarization and interconnect structures formed thereby 失效
    用于选择性反向掩模平面化和由此形成的互连结构的方法

    公开(公告)号：US08710661B2

    公开(公告)日：2014-04-29

    申请号：US12323512

    申请日：2008-11-26

    申请人： Zhong-Xiang He ,  Anthony K. Stamper ,  Eric J. White

    发明人： Zhong-Xiang He ,  Anthony K. Stamper ,  Eric J. White

    IPC分类号： H01L23/522

    CPC分类号： H01L23/528 ,  H01L21/31056 ,  H01L21/76819 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods for planarizing layers of a material, such as a dielectric, and interconnect structures formed by the planarization methods. The method includes depositing a first dielectric layer on a top surface of multiple conductive features and on a top surface of a substrate between the conductive features. A portion of the first dielectric layer is selectively removed from the top surface of at least one of the conductive features without removing a portion the first dielectric layer that is between the conductive features. A second dielectric layer is formed on the top surface of the at least one of the conductive features and on a top surface of the first dielectric layer, and a top surface of the second dielectric layer is planarized. A layer operating as an etch stop is located between the top surface of at least one of the conductive features and the second dielectric layer.

    摘要翻译： 用于平坦化诸如电介质的材料层的平面化方法以及通过平面化方法形成的互连结构。 该方法包括在多个导电特征的顶表面和导电特征之间的衬底的顶表面上沉积第一介电层。 第一介电层的一部分从至少一个导电特征的顶表面选择性地去除，而不去除导电特征之间的第一介电层的一部分。 第二电介质层形成在至少一个导电特征的顶表面上和第一介电层的顶表面上，并且第二介电层的顶表面被平坦化。 作为蚀刻停止件操作的层位于导电特征中的至少一个的顶表面和第二介电层之间。

    Method of electrolytic plating and semiconductor device fabrication
    3.
    发明授权
    Method of electrolytic plating and semiconductor device fabrication 有权
    电解电镀和半导体器件制造方法

    公开(公告)号：US08518817B2

    公开(公告)日：2013-08-27

    申请号：US12887737

    申请日：2010-09-22

    申请人： Felix P. Anderson ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Eric J. White

    发明人： Felix P. Anderson ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Eric J. White

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/7684 ,  C25D3/38 ,  C25D5/10 ,  C25D5/12 ,  H01L21/2885 ,  H01L21/76877

    摘要： The disclosure relates generally to semiconductor device fabrication, and more particularly to methods of electroplating used in semiconductor device fabrication. A method of electroplating includes: immersing an in-process substrate into an electrolytic plating solution to form a first metal layer on the in-process substrate; then performing a first chemical-mechanical polish to a liner on the in-process substrate followed by immersing the in-process substrate into the electrolytic plating solution to form a second metal layer on the first metal layer and the liner; and performing a second chemical-mechanical polish to the liner.

    摘要翻译： 本公开一般涉及半导体器件制造，更具体地涉及用于半导体器件制造中的电镀方法。 电镀方法包括：将处理后的基板浸入电解镀液中以在工艺衬底上形成第一金属层; 然后对所述工艺衬底上的衬垫进行第一化学机械抛光，然后将所述工艺衬底浸入所述电解电镀溶液中，以在所述第一金属层和所述衬垫上形成第二金属层; 以及对所述衬垫执行第二化学机械抛光。

    Slurryless Mechanical Planarization for Substrate Reclamation
    5.
    发明申请
    Slurryless Mechanical Planarization for Substrate Reclamation 有权
    无碴机械平面化基板回收

    公开(公告)号：US20090270017A1

    公开(公告)日：2009-10-29

    申请号：US12111276

    申请日：2008-04-29

    申请人： Graham M. Bates ,  David Domina ,  James L. Hardy, JR. ,  Eric J. White

    发明人： Graham M. Bates ,  David Domina ,  James L. Hardy, JR. ,  Eric J. White

    IPC分类号： B24B7/20 ,  H01L21/304

    CPC分类号： B24B7/228 ,  H01L21/02032 ,  H01L21/02079 ,  H01L21/31053 ,  H01L21/32115

    摘要： A patterned portion of a patterned semiconductor substrate is removed by abrasive mechanical planarization employing an abrasive pad but without employing any slurry. Preferably, water is supplied to enhance the removal rate during the mechanical planarization. The removal rate of material is substantially independent for common materials employed in back-end-of-line (BEOL) semiconductor materials, which enables non-selective removal of the material containing metallization structures. The removal rate of silicon is lower than the removal rate for the BEOL semiconductor materials, enabling a self-stopping planarization process.

    摘要翻译： 图案化半导体衬底的图案化部分通过使用研磨垫的磨料机械平面化除去，但不使用任何浆料。 优选地，在机械平面化期间供应水以提高去除率。 材料的去除速率对于后端行业（BEOL）半导体材料中采用的普通材料来说基本上是独立的，这使得能够非选择性地去除含有金属化结构的材料。 硅的去除率低于BEOL半导体材料的去除率，能够进行自我停止的平坦化处理。

    Process for producing crackstops on semiconductor devices and devices containing the crackstops
    6.
    发明授权
    Process for producing crackstops on semiconductor devices and devices containing the crackstops 失效
    在含有裂缝的半导体器件和器件上生产裂缝的工艺

    公开(公告)号：US5530280A

    公开(公告)日：1996-06-25

    申请号：US414889

    申请日：1995-03-31

    申请人： Eric J. White

    发明人： Eric J. White

    IPC分类号： H01L21/301 ,  H01L21/3205 ,  H01L23/00 ,  H01L23/52 ,  H01L21/265 ,  H01L21/308

    CPC分类号： H01L23/562 ,  H01L2924/0002 ,  H01L2924/13091

    摘要： A process for making a crackstop on a semiconductor device is disclosed. The process involves creating and metallizing a groove surrounding the active region on a chip at the same time as other functional metallization is occurring, and then selectively etching out the metal in the groove after final passivation. In various embodiments the groove passes through the surface dielectric or the semiconductor substrate. In one embodiment the groove is replaced by hollow metal rings that can be stacked through multiple dielectric layers.

    摘要翻译： 公开了一种在半导体器件上制作裂缝的工艺。 该过程涉及在发生其它功能性金属化的同时在芯片上产生和金属化围绕有源区的沟槽，然后在最终钝化之后选择性地蚀刻凹槽中的金属。 在各种实施例中，凹槽通过表面电介质或半导体衬底。 在一个实施例中，凹槽由可以通过多个介电层堆叠的中空金属环代替。

    Solution for forming polishing slurry, polishing slurry and related methods
    9.
    发明授权
    Solution for forming polishing slurry, polishing slurry and related methods 有权
    抛光浆，抛光浆及其相关方法的研究

    公开(公告)号：US08636917B2

    公开(公告)日：2014-01-28

    申请号：US12876518

    申请日：2010-09-07

    申请人： Joseph K. V. Comeau ,  Marina M. Katsnelson ,  Matthew T. Tiersch ,  Eric J. White

    发明人： Joseph K. V. Comeau ,  Marina M. Katsnelson ,  Matthew T. Tiersch ,  Eric J. White

    IPC分类号： C09K13/00

    CPC分类号： C09K3/1463 ,  C09G1/02 ,  C09G1/04

    摘要： A solution for forming a polishing slurry, the polishing slurry and related methods are disclosed. The solution for forming a polishing slurry may include 1H-benzotriazole (BTA) dissolved in an ionic surfactant such as a sodium alkyl sulfate solution, and perhaps a polyacrylic acid (PAA) solution. The solution can be filtered and used in a polishing slurry. This approach to solubilizing BTA results in a high BTA concentration in a polishing slurry without addition of foreign components to the slurry or increased safety hazard. In addition, the solution is easier to ship because it is very stable (e.g., can be frozen and thawed) and has less volume compared to conventional approaches. Further, the polishing slurry performance is vastly improved due to the removal of particles that can cause scratching.

    摘要翻译： 公开了一种用于形成抛光浆料，抛光浆料和相关方法的溶液。 用于形成抛光浆料的溶液可以包括溶解在诸如烷基硫酸钠溶液和可能的聚丙烯酸（PAA）溶液的离子表面活性剂中的1H-苯并三唑（BTA）。 该溶液可以过滤并用于抛光浆料中。 这种溶解BTA的方法导致抛光浆料中的高BTA浓度，而不会向浆料中添加外来成分或增加安全隐患。 此外，由于该溶液非常稳定（例如可以冷冻和解冻）并且与常规方法相比具有较少的体积，因此该溶液更易于运输。 此外，由于去除可能引起划伤的颗粒，抛光浆料性能大大提高。

    Slurryless mechanical planarization for substrate reclamation
    10.
    发明授权
    Slurryless mechanical planarization for substrate reclamation 有权
    无衬底机械平面化用于衬底回收

    公开(公告)号：US08210904B2

    公开(公告)日：2012-07-03

    申请号：US12111276

    申请日：2008-04-29

    申请人： Graham M. Bates ,  David Domina ,  James L. Hardy, Jr. ,  Eric J. White

    发明人： Graham M. Bates ,  David Domina ,  James L. Hardy, Jr. ,  Eric J. White

    IPC分类号： B24B1/00

    CPC分类号： B24B7/228 ,  H01L21/02032 ,  H01L21/02079 ,  H01L21/31053 ,  H01L21/32115

    摘要： A patterned portion of a patterned semiconductor substrate is removed by abrasive mechanical planarization employing an abrasive pad but without employing any slurry. Preferably, water is supplied to enhance the removal rate during the mechanical planarization. The removal rate of material is substantially independent for common materials employed in back-end-of-line (BEOL) semiconductor materials, which enables non-selective removal of the material containing metallization structures. The removal rate of silicon is lower than the removal rate for the BEOL semiconductor materials, enabling a self-stopping planarization process.

    摘要翻译： 图案化半导体衬底的图案化部分通过使用研磨垫的磨料机械平面化除去，但不使用任何浆料。 优选地，在机械平面化期间供应水以提高去除率。 材料的去除速率对于后端行业（BEOL）半导体材料中采用的普通材料来说基本上是独立的，这使得能够非选择性地去除含有金属化结构的材料。 硅的去除率低于BEOL半导体材料的去除率，能够进行自我停止的平坦化处理。