知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

51 条记录 (耗时 0.034 秒)

    Negative thermal expansion system (NTEs) device for TCE compensation in elastomer composites and conductive elastomer interconnects in microelectronic packaging
    7.
    发明授权
    Negative thermal expansion system (NTEs) device for TCE compensation in elastomer composites and conductive elastomer interconnects in microelectronic packaging 有权
    负热膨胀系统（NTE）装置用于弹性体复合材料中的TCE补偿和微电子封装中的导电弹性体互连

    公开(公告)号：US07417315B2

    公开(公告)日：2008-08-26

    申请号：US10310532

    申请日：2002-12-05

    申请人： Gareth Geoffrey Hougham ,  S. Jay Chey ,  James Patrick Doyle ,  Xiao Hu Liu ,  Christopher V. Jahnes ,  Paul Alfred Lauro ,  Nancy C. LaBianca ,  Michael J. Rooks

    发明人： Gareth Geoffrey Hougham ,  S. Jay Chey ,  James Patrick Doyle ,  Xiao Hu Liu ,  Christopher V. Jahnes ,  Paul Alfred Lauro ,  Nancy C. LaBianca ,  Michael J. Rooks

    IPC分类号： H01L21/302 ,  B32B5/22 ,  G02B26/00

    CPC分类号： B81B3/0035 ,  H01L2924/0002 ,  Y10T428/249986 ,  H01L2924/00

    摘要： A Negative Thermal Expansion system (NTEs) device for TCE compensation or CTE compensation in elastomer composites and conductive elastomer interconnects in microelectronic packaging. One aspect of the present invention provides a method for fabricating micromachine devices that have negative thermal expansion coefficients that can be made into a composite for manipulation of the TCE of the material. These devices and composites made with these devices are in the categories of materials called “smart materials” or “responsive materials.” Another aspect of the present invention provides microdevices comprised of dual opposed bilayers of material where the two bilayers are attached to one another at the peripheral edges only, and where the bilayers themselves are at a minimum stress conditions at a reference temperature defined by the temperature at which the bilayers are formed. These devices have the technologically useful property of volumetrically expanding upon lowering of the device temperature below the reference or processing temperature.

    摘要翻译： 用于微电子封装中弹性体复合材料和导电弹性体互连的TCE补偿或CTE补偿的负热膨胀系统（NTE）装置。 本发明的一个方面提供了一种用于制造具有负热膨胀系数的微机械装置的方法，该热膨胀系数可以制成用于操纵材料的TCE的复合材料。 这些设备和这些设备制成的复合材料属于称为“智能材料”或“响应材料”的材料类别。 本发明的另一方面提供了由双重相对的双层材料构成的微器件，其中两个双层仅在外围边缘处彼此附接，并且其中双层本身处于由温度定义的参考温度下的最小应力条件 双层形成。 当器件温度降低到参考温度或加工温度以下时，这些器件具有技术上有用的特性。

    Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same
    10.
    发明授权
    Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same 失效
    具有低介电常数绝缘体的芯片互连布线结构及其制造方法

    公开(公告)号：US06184121B2

    公开(公告)日：2001-02-06

    申请号：US09112919

    申请日：1998-07-09

    申请人： Leena P. Buchwalter ,  Alessandro Cesare Callegari ,  Stephan Alan Cohen ,  Teresita Ordonez Graham ,  John P. Hummel ,  Christopher V. Jahnes ,  Sampath Purushothaman ,  Katherine Lynn Saenger ,  Jane Margaret Shaw

    发明人： Leena P. Buchwalter ,  Alessandro Cesare Callegari ,  Stephan Alan Cohen ,  Teresita Ordonez Graham ,  John P. Hummel ,  Christopher V. Jahnes ,  Sampath Purushothaman ,  Katherine Lynn Saenger ,  Jane Margaret Shaw

    IPC分类号： H01L214763

    CPC分类号： H01L23/53228 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method to achieve a very low effective dielectric constant in high performance back end of the line chip interconnect wiring and the resulting multilayer structure are disclosed. The process involves fabricating the multilayer interconnect wiring structure by methods and materials currently known in the state of the art of semiconductor processing; removing the intralevel dielectric between the adjacent metal features by a suitable etching process; applying a thin passivation coating over the exposed etched structure; annealing the etched structure to remove plasma damage; laminating an insulating cover layer to the top surface of the passivated metal features; optionally depositing an insulating environmental barrier layer on top of the cover layer; etching vias in the environmental barrier layer, cover layer and the thin passivation layer for terminal pad contacts; and completing the device by fabricating terminal input/output pads. The method obviates issues such as processability and thermal stability associated with low dielectric constant materials by avoiding their use. Since air, which has the lowest dielectric constant, is used as the intralevel dielectric the structure created by this method would possess a very low capacitance and hence fast propagation speeds. Such structure is ideally suitable for high density interconnects required in high performance microelectronic device chips.

    摘要翻译： 公开了一种在线芯片互连布线和所得多层结构的高性能后端中实现非常低的有效介电常数的方法。 该方法涉及通过目前在半导体处理领域中已知的方法和材料制造多层互连布线结构; 通过合适的蚀刻工艺去除相邻金属特征之间的层间电介质; 在暴露的蚀刻结构上施加薄的钝化涂层; 退火蚀刻结构以去除等离子体损伤; 将绝缘覆盖层层压到钝化金属特征的顶表面; 可选地在覆盖层的顶部上沉积绝缘环境阻挡层; 在环境阻挡层，覆盖层和用于端子焊盘触点的薄钝化层中蚀刻通孔; 并通过制造端子输入/输出焊盘来完成该器件。 该方法通过避免其使用而消除了与低介电常数材料相关的加工性和热稳定性等问题。 由于具有最低介电常数的空气被用作体内电介质，所以通过该方法产生的结构将具有非常低的电容并因此具有快速的传播速度。 这种结构理想地适用于高性能微电子器件芯片所需的高密度互连。