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公开(公告)号：US20120070979A1
公开(公告)日：2012-03-22
申请号：US12887737
申请日：2010-09-22
IPC分类号： H01L21/768 , C25D5/12 , C25D5/14 , H01L21/02
CPC分类号： H01L21/7684 , C25D3/38 , C25D5/10 , C25D5/12 , H01L21/2885 , H01L21/76877
摘要： The disclosure relates generally to semiconductor device fabrication, and more particularly to methods of electroplating used in semiconductor device fabrication. A method of electroplating includes: immersing an in-process substrate into an electrolytic plating solution to form a first metal layer on the in-process substrate; then performing a first chemical-mechanical polish to a liner on the in-process substrate followed by immersing the in-process substrate into the electrolytic plating solution to form a second metal layer on the first metal layer and the liner; and performing a second chemical-mechanical polish to the liner.
摘要翻译： 本公开一般涉及半导体器件制造，更具体地涉及用于半导体器件制造中的电镀方法。 电镀方法包括：将处理后的基板浸入电解镀液中以在工艺衬底上形成第一金属层; 然后对所述工艺衬底上的衬垫进行第一化学机械抛光，然后将所述工艺衬底浸入所述电解电镀溶液中，以在所述第一金属层和所述衬垫上形成第二金属层; 以及对所述衬垫执行第二化学机械抛光。
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2.发明授权Planar cavity MEMS and related structures, methods of manufacture and design structures 有权平面腔MEMS及相关结构，制造方法和设计结构公开(公告)号：US09406472B2
公开(公告)日：2016-08-02
申请号：US12974854
申请日：2010-12-21
申请人： Dinh Dang , Thai Doan , George A. Dunbar, III , Zhong-Xiang He , Russell T. Herrin , Christopher V. Jahnes , Jeffrey C. Maling , William J. Murphy , Anthony K. Stamper , John G. Twombly , Eric J. White
发明人： Dinh Dang , Thai Doan , George A. Dunbar, III , Zhong-Xiang He , Russell T. Herrin , Christopher V. Jahnes , Jeffrey C. Maling , William J. Murphy , Anthony K. Stamper , John G. Twombly , Eric J. White
IPC分类号： B81C1/00 , H01H59/00 , H01L21/768 , H01L41/113 , H01H57/00 , B81B3/00 , G06F17/50 , H01H1/00
CPC分类号： B81B3/0072 , B81B3/0021 , B81B2201/01 , B81B2201/014 , B81B2203/0118 , B81B2203/0315 , B81B2203/04 , B81C1/0015 , B81C1/00365 , B81C1/00476 , B81C1/00619 , B81C1/00626 , B81C1/00666 , B81C2201/0109 , B81C2201/013 , B81C2201/0167 , B81C2201/017 , B81C2203/0136 , B81C2203/0172 , G06F17/5068 , G06F17/5072 , H01H1/0036 , H01H57/00 , H01H59/0009 , H01H2057/006 , H01L41/1136 , H01L2924/0002 , Y10S438/937 , Y10T29/42 , Y10T29/435 , Y10T29/49002 , Y10T29/49105 , Y10T29/49121 , Y10T29/49126 , Y10T29/4913 , Y10T29/49155 , Y10T29/5313 , H01L2924/00
摘要： Planar cavity Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structure are provided. The method includes forming at least one Micro-Electro-Mechanical System (MEMS) cavity having a planar surface using a reverse damascene process.
摘要翻译： 提供了平面腔微机电系统（MEMS）结构，制造方法和设计结构。 该方法包括使用反向镶嵌工艺形成具有平面表面的至少一个微机电系统（MEMS）空腔。
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3.发明授权Methods for selective reverse mask planarization and interconnect structures formed thereby 失效用于选择性反向掩模平面化和由此形成的互连结构的方法公开(公告)号：US08710661B2
公开(公告)日：2014-04-29
申请号：US12323512
申请日：2008-11-26
IPC分类号： H01L23/522
CPC分类号： H01L23/528 , H01L21/31056 , H01L21/76819 , H01L2924/0002 , H01L2924/00
摘要： Methods for planarizing layers of a material, such as a dielectric, and interconnect structures formed by the planarization methods. The method includes depositing a first dielectric layer on a top surface of multiple conductive features and on a top surface of a substrate between the conductive features. A portion of the first dielectric layer is selectively removed from the top surface of at least one of the conductive features without removing a portion the first dielectric layer that is between the conductive features. A second dielectric layer is formed on the top surface of the at least one of the conductive features and on a top surface of the first dielectric layer, and a top surface of the second dielectric layer is planarized. A layer operating as an etch stop is located between the top surface of at least one of the conductive features and the second dielectric layer.
摘要翻译： 用于平坦化诸如电介质的材料层的平面化方法以及通过平面化方法形成的互连结构。 该方法包括在多个导电特征的顶表面和导电特征之间的衬底的顶表面上沉积第一介电层。 第一介电层的一部分从至少一个导电特征的顶表面选择性地去除，而不去除导电特征之间的第一介电层的一部分。 第二电介质层形成在至少一个导电特征的顶表面上和第一介电层的顶表面上，并且第二介电层的顶表面被平坦化。 作为蚀刻停止件操作的层位于导电特征中的至少一个的顶表面和第二介电层之间。
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公开(公告)号：US08518817B2
公开(公告)日：2013-08-27
申请号：US12887737
申请日：2010-09-22
IPC分类号： H01L21/4763
CPC分类号： H01L21/7684 , C25D3/38 , C25D5/10 , C25D5/12 , H01L21/2885 , H01L21/76877
摘要： The disclosure relates generally to semiconductor device fabrication, and more particularly to methods of electroplating used in semiconductor device fabrication. A method of electroplating includes: immersing an in-process substrate into an electrolytic plating solution to form a first metal layer on the in-process substrate; then performing a first chemical-mechanical polish to a liner on the in-process substrate followed by immersing the in-process substrate into the electrolytic plating solution to form a second metal layer on the first metal layer and the liner; and performing a second chemical-mechanical polish to the liner.
摘要翻译： 本公开一般涉及半导体器件制造，更具体地涉及用于半导体器件制造中的电镀方法。 电镀方法包括：将处理后的基板浸入电解镀液中以在工艺衬底上形成第一金属层; 然后对所述工艺衬底上的衬垫进行第一化学机械抛光，然后将所述工艺衬底浸入所述电解电镀溶液中，以在所述第一金属层和所述衬垫上形成第二金属层; 以及对所述衬垫执行第二化学机械抛光。
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公开(公告)号：US08093679B2
公开(公告)日：2012-01-10
申请号：US13023579
申请日：2011-02-09
申请人： Anil K. Chinthakindi , Douglas D. Coolbaugh , John M. Cotte , Ebenezer E. Eshun , Zhong-Xiang He , Anthony K. Stamper , Eric J. White
发明人： Anil K. Chinthakindi , Douglas D. Coolbaugh , John M. Cotte , Ebenezer E. Eshun , Zhong-Xiang He , Anthony K. Stamper , Eric J. White
CPC分类号： H01L23/5228 , H01L2924/0002 , H01L2924/00
摘要： In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers.
摘要翻译： 在集成电路的后端形成电阻器的过程中，沉积中间介电层，并通过可蚀刻的量蚀刻通过该介质层并将其沉积到下介电层中，使得沉积在电介质层中的电阻层的顶部 沟槽的高度接近于下介电层的顶部; 沟槽被填充，沟槽外的电阻层被去除，然后沉积第二介电层。 通过第二电介质层以与电阻器接触的通孔的深度与下电介质层中的金属互连接触孔的深度相同。 使用三层电阻器结构，其中电阻膜夹在两个阻挡电阻器和BEOL ILD层之间的扩散的保护层之间。
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公开(公告)号：US07902629B2
公开(公告)日：2011-03-08
申请号：US12271942
申请日：2008-11-17
申请人： Anil K. Chinthakindi , Douglas D. Coolbaugh , John M. Cotte , Ebenezer E. Eshun , Zhong-Xiang He , Anthony K. Stamper , Eric J. White
发明人： Anil K. Chinthakindi , Douglas D. Coolbaugh , John M. Cotte , Ebenezer E. Eshun , Zhong-Xiang He , Anthony K. Stamper , Eric J. White
CPC分类号： H01L23/5228 , H01L2924/0002 , H01L2924/00
摘要： In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers.
摘要翻译： 在集成电路的后端形成电阻器的过程中，沉积中间介电层，并通过可蚀刻的量蚀刻通过该介质层并将其沉积到下介电层中，使得沉积在电介质层中的电阻层的顶部 沟槽的高度接近于下介电层的顶部; 沟槽被填充，沟槽外的电阻层被去除，然后沉积第二介电层。 通过第二电介质层以与电阻器接触的通孔的深度与下电介质层中的金属互连接触孔的深度相同。 使用三层电阻器结构，其中电阻膜夹在两个阻挡电阻器和BEOL ILD层之间的扩散的保护层之间。
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公开(公告)号：US20090065898A1
公开(公告)日：2009-03-12
申请号：US12271942
申请日：2008-11-17
申请人： Anil K. Chinthakindi , Douglas D. Coolbaugh , John M. Cotte , Ebenezer E. Eshun , Zhong-Xiang He , Anthony K. Stamper , Eric J. White
发明人： Anil K. Chinthakindi , Douglas D. Coolbaugh , John M. Cotte , Ebenezer E. Eshun , Zhong-Xiang He , Anthony K. Stamper , Eric J. White
IPC分类号： H01L29/00
CPC分类号： H01L23/5228 , H01L2924/0002 , H01L2924/00
摘要： In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers.
摘要翻译： 在集成电路的后端形成电阻器的过程中，沉积中间介电层，并通过可蚀刻的量蚀刻通过该介质层并将其沉积到下介电层中，使得沉积在电介质层中的电阻层的顶部 沟槽的高度接近于下介电层的顶部; 沟槽被填充，沟槽外的电阻层被去除，然后沉积第二介电层。 通过第二电介质层以与电阻器接触的通孔的深度与下电介质层中的金属互连接触孔的深度相同。 使用三层电阻器结构，其中电阻膜夹在两个阻挡电阻器和BEOL ILD层之间的扩散的保护层之间。
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公开(公告)号：US07485540B2
公开(公告)日：2009-02-03
申请号：US11161832
申请日：2005-08-18
申请人： Anil K. Chinthakindi , Douglas D. Coolbaugh , John M. Cotte , Ebenezer E. Eshun , Zhong-Xiang He , Anthony K. Stamper , Eric J. White
发明人： Anil K. Chinthakindi , Douglas D. Coolbaugh , John M. Cotte , Ebenezer E. Eshun , Zhong-Xiang He , Anthony K. Stamper , Eric J. White
IPC分类号： H01L21/20
CPC分类号： H01L23/5228 , H01L2924/0002 , H01L2924/00
摘要： In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers.
摘要翻译： 在集成电路的后端形成电阻器的过程中，沉积中间介电层，并通过可蚀刻的量蚀刻通过该介质层并将其沉积到下介电层中，使得沉积在电介质层中的电阻层的顶部 沟槽的高度接近于下介电层的顶部; 沟槽被填充，沟槽外的电阻层被去除，然后沉积第二介电层。 通过第二电介质层以与电阻器接触的通孔的深度与下电介质层中的金属互连接触孔的深度相同。 使用三层电阻器结构，其中电阻膜夹在两个阻挡电阻器和BEOL ILD层之间的扩散的保护层之间。
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公开(公告)号：US20110127635A1
公开(公告)日：2011-06-02
申请号：US13023579
申请日：2011-02-09
申请人： Anil K. Chinthakindi , Douglas D. Coolbaugh , John M. Cotte , Ebenezer E. Eshun , Zhong-Xiang He , Anthony K. Stamper , Eric J. White
发明人： Anil K. Chinthakindi , Douglas D. Coolbaugh , John M. Cotte , Ebenezer E. Eshun , Zhong-Xiang He , Anthony K. Stamper , Eric J. White
IPC分类号： H01L23/58
CPC分类号： H01L23/5228 , H01L2924/0002 , H01L2924/00
摘要： In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers.
摘要翻译： 在集成电路的后端形成电阻器的过程中，沉积中间介电层，并通过可蚀刻的量蚀刻通过该介质层并将其沉积到下介电层中，使得沉积在电介质层中的电阻层的顶部 沟槽的高度接近于下介电层的顶部; 沟槽被填充，沟槽外的电阻层被去除，然后沉积第二介电层。 通过第二电介质层以与电阻器接触的通孔的深度与下电介质层中的金属互连接触孔的深度相同。 使用三层电阻器结构，其中电阻膜夹在两个阻挡电阻器和BEOL ILD层之间的扩散的保护层之间。
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10.发明申请公开(公告)号：US20100127395A1
公开(公告)日：2010-05-27
申请号：US12323512
申请日：2008-11-26
IPC分类号： H01L21/768 , H01L23/522
CPC分类号： H01L23/528 , H01L21/31056 , H01L21/76819 , H01L2924/0002 , H01L2924/00
摘要： Methods for planarizing layers of a material, such as a dielectric, and interconnect structures formed by the planarization methods. The method includes depositing a first dielectric layer on a top surface of multiple conductive features and on a top surface of a substrate between the conductive features. A portion of the first dielectric layer is selectively removed from the top surface of at least one of the conductive features without removing a portion the first dielectric layer that is between the conductive features. A second dielectric layer is formed on the top surface of the at least one of the conductive features and on a top surface of the first dielectric layer, and a top surface of the second dielectric layer is planarized. A layer operating as an etch stop is located between the top surface of at least one of the conductive features and the second dielectric layer.
摘要翻译： 用于平坦化诸如电介质的材料层的平面化方法以及通过平面化方法形成的互连结构。 该方法包括在多个导电特征的顶表面和导电特征之间的衬底的顶表面上沉积第一介电层。 第一介电层的一部分从至少一个导电特征的顶表面选择性地去除，而不去除导电特征之间的第一介电层的一部分。 第二电介质层形成在至少一个导电特征的顶表面上和第一介电层的顶表面上，并且第二介电层的顶表面被平坦化。 作为蚀刻停止件操作的层位于导电特征中的至少一个的顶表面和第二介电层之间。
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