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    REDUCING DAMAGE TO ULK DIELECTRIC DURING CROSS-LINKED POLYMER REMOVAL
    2.
    发明申请
    REDUCING DAMAGE TO ULK DIELECTRIC DURING CROSS-LINKED POLYMER REMOVAL 有权
    在交联聚合物去除期间减少对ULK电介质的损伤

    公开(公告)号：US20070111466A1

    公开(公告)日：2007-05-17

    申请号：US11164290

    申请日：2005-11-17

    申请人： Ronald DellaGuardia ,  Daniel Edelstein ,  Habib Hichri ,  Vincent McGahay

    发明人： Ronald DellaGuardia ,  Daniel Edelstein ,  Habib Hichri ,  Vincent McGahay

    IPC分类号： H01L21/76

    CPC分类号： H01L21/31144 ,  H01L21/02063 ,  H01L21/31133 ,  H01L21/76808

    摘要： Methods are disclosed for reducing damage to an ultra-low dielectric constant (ULK) dielectric during removal of a planarizing layer such as a crosslinked polymer. The methods at least partially fill an opening with an at most lightly crosslinked polymer, followed by the planarizing layer. When the at most lightly crosslinked polymer and planarizing layer are removed, the at most lightly crosslinked polymer removal is easier than removal of the planarizing layer, i.e., crosslinked polymer, and does not damage the surrounding dielectric compared to removal chemistries used for the crosslinked polymer.

    摘要翻译： 公开了减少在去除平坦化层例如交联聚合物期间对超低介电常数（ULK）电介质的损伤的方法。 该方法至少部分地用至少轻度交联的聚合物填充开口，随后是平坦化层。 当除去至多轻度交联的聚合物和平坦化层时，与用于交联聚合物的去除化学物质相比，去除至多轻度交联的聚合物去除比去除平坦化层即交联聚合物更容易，并且不损坏周围的电介质 。

    COMPLIANT PASSIVATED EDGE SEAL FOR LOW-K INTERCONNECT STRUCTURES
    3.
    发明申请
    COMPLIANT PASSIVATED EDGE SEAL FOR LOW-K INTERCONNECT STRUCTURES 有权
    适用于低K互连结构的合适封闭边缘密封

    公开(公告)号：US20060281224A1

    公开(公告)日：2006-12-14

    申请号：US11464959

    申请日：2006-08-16

    申请人： Daniel Edelstein ,  Lee Nicholson

    发明人： Daniel Edelstein ,  Lee Nicholson

    IPC分类号： H01L21/00 ,  H01L23/48

    CPC分类号： H01L23/3135 ,  H01L23/3121 ,  H01L23/3178 ,  H01L23/3185 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2224/29099 ,  H01L2924/00

    摘要： A structure for a chip or chip package is disclosed, with final passivation and terminal metallurgy which are mechanically decoupled but electrically coupled to the multilayer on-chip interconnects. This decoupling allows the chip to survive packaging stresses in the final passivation region, with strain relief from the decoupling region and compliant leads therein, so that on-chip interconnect levels do not feel these external packaging or other stresses. This structure is particularly preferred for on-chip interconnects consisting of Cu and low-k dielectric, the latter having inferior mechanical properties relative to SiO2. The decoupled region extends over all chips on the wafer. It may also extend into the edgeseal or dicing channel region so as to allow chip dicing and retention of this mechanical decoupling all around every chip on the wafer.

    摘要翻译： 公开了一种用于芯片或芯片封装的结构，其具有机械去耦合但电耦合到多层片上互连的最终钝化和终端冶金。 这种去耦允许芯片在最终钝化区域中经受包装应力，在去耦区域和柔性引线处具有应变消除，使得片上互连电平不会感受到这些外部封装或其他应力。 对于由Cu和低k电介质组成的片上互连，该结构特别优选，后者相对于SiO 2具有差的机械性能。 去耦区延伸在晶片上的所有芯片上。 它也可以延伸到edgeseal或切割通道区域，以便允许在晶片上的每个芯片周围进行芯片切割和保持这种机械解耦。

    Apparatus and method for thermal isolation, circuit cooling and electromagnetic shielding of a wafer
    7.
    发明申请
    Apparatus and method for thermal isolation, circuit cooling and electromagnetic shielding of a wafer 有权
    晶片的隔热，电路冷却和电磁屏蔽的装置和方法

    公开(公告)号：US20050282381A1

    公开(公告)日：2005-12-22

    申请号：US10872451

    申请日：2004-06-22

    申请人： Guy Cohen ,  Daniel Edelstein ,  Keith Jenkins ,  Chirag Patel ,  Lie Shan

    发明人： Guy Cohen ,  Daniel Edelstein ,  Keith Jenkins ,  Chirag Patel ,  Lie Shan

    IPC分类号： H01L21/4763 ,  H01L21/76 ,  H01L23/367

    CPC分类号： H01L23/552 ,  H01L23/3677 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： The disclosure relates to method and apparatus for isolating sensitive regions of a semiconductor device by providing a thermal path or an electromagnetic shield. The thermal path may include vias having different length, depth and configuration such that the thermal path between the two regions is lengthened. In addition, the vias may be fully or partially filled with an insulating material having defined conductive properties to further retard heat electromagnetic or heat transmission between the regions. In another embodiment, electrical isolation between two regions is achieved by etching a closed loop or an open loop trench at the border of the regions and filling the trench with a conductive material to provide proper termination of electromagnetic fields within the substrate.

    摘要翻译： 本公开涉及通过提供热路径或电磁屏蔽来隔离半导体器件的敏感区域的方法和装置。 热路径可以包括具有不同长度，深度和构造的通孔，使得两个区域之间的热路径被延长。 此外，通孔可以被完全或部分地填充有具有确定的导电性质的绝缘材料，以进一步延缓区域之间的热电磁或热传递。 在另一个实施例中，通过在区域的边界处蚀刻闭环或开环沟槽并用导电材料填充沟槽来实现两个区域之间的电隔离，以提供衬底内电磁场的适当终止。