公开(公告)号：US20060281224A1

公开(公告)日：2006-12-14

申请号：US11464959

申请日：2006-08-16

申请人： Daniel Edelstein ,  Lee Nicholson

发明人： Daniel Edelstein ,  Lee Nicholson

IPC分类号： H01L21/00 ,  H01L23/48

CPC分类号： H01L23/3135 ,  H01L23/3121 ,  H01L23/3178 ,  H01L23/3185 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2224/29099 ,  H01L2924/00

摘要： A structure for a chip or chip package is disclosed, with final passivation and terminal metallurgy which are mechanically decoupled but electrically coupled to the multilayer on-chip interconnects. This decoupling allows the chip to survive packaging stresses in the final passivation region, with strain relief from the decoupling region and compliant leads therein, so that on-chip interconnect levels do not feel these external packaging or other stresses. This structure is particularly preferred for on-chip interconnects consisting of Cu and low-k dielectric, the latter having inferior mechanical properties relative to SiO2. The decoupled region extends over all chips on the wafer. It may also extend into the edgeseal or dicing channel region so as to allow chip dicing and retention of this mechanical decoupling all around every chip on the wafer.

摘要翻译： 公开了一种用于芯片或芯片封装的结构，其具有机械去耦合但电耦合到多层片上互连的最终钝化和终端冶金。 这种去耦允许芯片在最终钝化区域中经受包装应力，在去耦区域和柔性引线处具有应变消除，使得片上互连电平不会感受到这些外部封装或其他应力。 对于由Cu和低k电介质组成的片上互连，该结构特别优选，后者相对于SiO 2具有差的机械性能。 去耦区延伸在晶片上的所有芯片上。 它也可以延伸到edgeseal或切割通道区域，以便允许在晶片上的每个芯片周围进行芯片切割和保持这种机械解耦。

公开(公告)号：US20050167838A1

公开(公告)日：2005-08-04

申请号：US10707996

申请日：2004-01-30

申请人： Daniel Edelstein ,  Matthew Colburn ,  Edward Cooney ,  Timothy Dalton ,  John Fitzsimmons ,  Jeffrey Gambino ,  Elbert Huang ,  Michael Lane ,  Vincent McGahay ,  Lee Nicholson ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas Shaw ,  Andrew Simon ,  Anthony Stamper

发明人： Daniel Edelstein ,  Matthew Colburn ,  Edward Cooney ,  Timothy Dalton ,  John Fitzsimmons ,  Jeffrey Gambino ,  Elbert Huang ,  Michael Lane ,  Vincent McGahay ,  Lee Nicholson ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas Shaw ,  Andrew Simon ,  Anthony Stamper

IPC分类号： H01L21/033 ,  H01L21/302 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532 ,  H01L29/40

CPC分类号： B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： A method for manufacturing a structure includes providing a structure having an insulator layer with at least one interconnect and forming a sub lithographic template mask on the insulator layer. A selective etching step is used for etching the insulator layer through the sub lithographic template mask to form sub lithographic features near the at least one interconnect. A supra lithographic blocking mask may also be utilized. In another aspect, the method includes forming pinch off sections of sub lithographic size formed in a capping layer on the insulator layer. A semiconductor structure includes an insulator layer having at least one interconnect feature and at least one column formed in the insulator layer. A plurality of sub lithographic features formed on a top portion of the insulator layer and communicating with the at least one column is also provided. The plurality of sub lithographic features have a cross section or diameter less than any of the at least one column. A gap may be prohibited from forming on or near scribe lanes and vias

摘要翻译： 一种制造结构的方法包括提供具有至少一个互连的绝缘层的结构，并在绝缘体层上形成次光刻模板掩模。 选择性蚀刻步骤用于通过子光刻模板掩模蚀刻绝缘体层，以在至少一个互连附近形成亚光刻特征。 还可以使用超光刻阻挡掩模。 另一方面，该方法包括形成在绝缘体层上的覆盖层中形成的亚光刻尺寸的夹断部分。 半导体结构包括具有至少一个互连特征的绝缘体层和形成在绝缘体层中的至少一个列。 还提供了形成在绝缘体层的顶部并与至少一个柱连通的多个次级光刻特征。 所述多个亚光刻特征具有小于或小于所述至少一列中的任何一个的横截面或直径。 可能禁止在划线车道和通道上或附近形成间隙

公开(公告)号：US20050145994A1

公开(公告)日：2005-07-07

申请号：US10707713

申请日：2004-01-06

申请人： Daniel Edelstein ,  Lee Nicholson

发明人： Daniel Edelstein ,  Lee Nicholson

IPC分类号： H01L23/31 ,  H01L21/44 ,  H01L23/58

CPC分类号： H01L23/3135 ,  H01L23/3121 ,  H01L23/3178 ,  H01L23/3185 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2224/29099 ,  H01L2924/00

摘要： A structure for a chip or chip package is disclosed, with final passivation and terminal metallurgy which are mechanically decoupled but electrically coupled to the multilayer on-chip interconnects. This decoupling allows the chip to survive packaging stresses in the final passivation region, with strain relief from the decoupling region and compliant leads therein, so that on-chip interconnect levels do not feel these external packaging or other stresses. This structure is particularly preferred for on-chip interconnects consisting of Cu and low-k dielectric, the latter having inferior mechanical properties relative to SiO2. The decoupled region extends over all chips on the wafer. It may also extend into the edgeseal or dicing channel region so as to allow chip dicing and retention of this mechanical decoupling all around every chip on the wafer.

摘要翻译： 公开了一种用于芯片或芯片封装的结构，其具有机械去耦合但电耦合到多层片上互连的最终钝化和终端冶金。 这种去耦允许芯片在最终钝化区域中经受包装应力，在去耦区域和柔性引线处具有应变消除，使得片上互连电平不会感受到这些外部封装或其他应力。 对于由Cu和低k电介质组成的片上互连，该结构特别优选，后者相对于SiO 2具有差的机械性能。 去耦区延伸在晶片上的所有芯片上。 它也可以延伸到edgeseal或切割通道区域，以便允许在晶片上的每个芯片周围进行芯片切割和保持这种机械解耦。

公开(公告)号：US20060027929A1

公开(公告)日：2006-02-09

申请号：US11247818

申请日：2005-10-11

申请人： Edward Cooney ,  John Fitzsimmons ,  Jeffrey Gambino ,  Stephen Luce ,  Thomas McDevitt ,  Lee Nicholson ,  Anthony Stamper

发明人： Edward Cooney ,  John Fitzsimmons ,  Jeffrey Gambino ,  Stephen Luce ,  Thomas McDevitt ,  Lee Nicholson ,  Anthony Stamper

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L23/58

CPC分类号： H01L21/76831 ,  H01L21/02107 ,  H01L21/02203 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/3105 ,  H01L21/31116 ,  H01L21/31695 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76868

摘要： Methods and structures having pore-closing layers for closing exposed pores in a patterned porous low-k dielectric layer, and optionally a reactive liner on the low-k dielectric. A first reactant is absorbed or retained in exposed pores in the patterned dielectric layer and then a second reactant is introduced into openings such that it enters the exposed-pores, while first reactant molecules are simultaneously being outgassed. The second reactant reacts in-situ with the outgassed first reactant molecules at a mouth region of the exposed pores to form the pore-closing layer across the mouth region of exposed pores, while retaining a portion of each pore's porosity to maintain characteristics and properties of the porous low-k dielectric layer. Optionally, the first reactant may be adsorbed onto the low-k dielectric such that upon introduction of the second reactant Into the patterned dielectric openings, a reactive liner is also formed on the low-k dielectric.

公开(公告)号：USD755670S1

公开(公告)日：2016-05-10

申请号：US29504993

申请日：2014-10-10

申请人： Lee Nicholson

设计人： Lee Nicholson

公开(公告)号：US20050023689A1

公开(公告)日：2005-02-03

申请号：US10628925

申请日：2003-07-28

申请人： Lee Nicholson ,  Wei-Tsu Tseng ,  Christy Tyberg

发明人： Lee Nicholson ,  Wei-Tsu Tseng ,  Christy Tyberg

IPC分类号： H01L21/283 ,  H01L21/304 ,  H01L21/31 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48

CPC分类号： H01L23/5329 ,  H01L21/76807 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/7684 ,  H01L21/7688 ,  H01L2924/0002 ,  Y10T428/31663 ,  H01L2924/00

摘要： An electrical interconnect structure on a substrate, which includes: a first low-k dielectric layer; a spin-on low k CMP protective layer that is covalently bonded to the first low-k dielectric layer; and a CVD deposited hardmask/CMP polish stop layer is provided. Electrical vias and lines can be formed in the first low k dielectric layer. The spin-on low k CMP protective layer prevents damage to the low k dielectric which can be created due to non-uniformity in the CMP process from center to edge or in areas of varying metal density. The thickness of the low-k CMP protective layer can be adjusted to accommodate larger variations in the CMP process without significantly impacting the effective dielectric constant of the structure.

摘要翻译： 在基板上的电互连结构，其包括：第一低k电介质层; 共价键合到第一低k电介质层的自旋低k CMP保护层; 并提供CVD沉积的硬掩模/ CMP抛光停止层。 可以在第一低k电介质层中形成电通孔和线。 旋转低k CMP保护层可防止由于中心到边缘或不同金属密度区域的CMP工艺中的不均匀性而导致的低k电介质的损坏。 可以调节低k CMP保护层的厚度以适应CMP工艺中的较大变化，而不显着影响结构的有效介电常数。

公开(公告)号：USD373808S

公开(公告)日：1996-09-17

申请号：US38085

申请日：1995-04-28

申请人： Lee Nicholson

设计人： Lee Nicholson

公开(公告)号：US20050266698A1

公开(公告)日：2005-12-01

申请号：US10709747

申请日：2004-05-26

申请人： Edward Cooney ,  John Fitzsimmons ,  Jeffrey Gambino ,  Stephen Luce ,  Thomas McDevitt ,  Lee Nicholson ,  Anthony Stamper

发明人： Edward Cooney ,  John Fitzsimmons ,  Jeffrey Gambino ,  Stephen Luce ,  Thomas McDevitt ,  Lee Nicholson ,  Anthony Stamper

IPC分类号： H01L21/31 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/316 ,  H01L21/469 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/76831 ,  H01L21/02107 ,  H01L21/02203 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/3105 ,  H01L21/31116 ,  H01L21/31695 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76868

摘要： Methods and structures having pore-closing layers for closing exposed pores in a patterned porous low-k dielectric layer, and optionally a reactive liner on the low-k dielectric. A first reactant is absorbed or retained in exposed pores in the patterned dielectric layer and then a second reactant is introduced into openings such that it enters the exposed pores, while first reactant molecules are simultaneously being outgassed. The second reactant reacts in-situ with the outgassed first reactant molecules at a mouth region of the exposed pores to form the pore-closing layer across the mouth region of exposed pores, while retaining a portion of each pore's porosity to maintain characteristics and properties of the porous low-k dielectric layer. Optionally, the first reactant may be adsorbed onto the low-k dielectric such that upon introduction of the second reactant into the patterned dielectric openings, a reactive liner is also formed on the low-k dielectric.

摘要翻译： 具有闭孔层的方法和结构，用于封闭图案化的多孔低k电介质层中的暴露孔，以及可选地在低k电介质上的反应性衬垫。 第一反应物被吸收或保留在图案化介电层中的暴露孔中，然后将第二反应物引入开口中，使得其进入暴露的孔，同时第一反应物分子同时脱气。 第二反应物与暴露孔的口部区域处的脱气的第一反应物分子原位反应，以形成穿过暴露孔的口部区域的孔闭合层，同时保留每个孔隙的一部分以保持其孔的特性和性质 多孔低k电介质层。 任选地，第一反应物可以被吸附到低k电介质上，使得当将第二反应物引入图案化的电介质开口中时，还在低k电介质上形成反应性衬垫。

公开(公告)号：US20060166012A1

公开(公告)日：2006-07-27

申请号：US11369476

申请日：2006-03-07

申请人： Lee Nicholson ,  Wei-Tsu Tseng ,  Christy Tyberg

发明人： Lee Nicholson ,  Wei-Tsu Tseng ,  Christy Tyberg

IPC分类号： B32B9/04

CPC分类号： H01L23/5329 ,  H01L21/76807 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/7684 ,  H01L21/7688 ,  H01L2924/0002 ,  Y10T428/31663 ,  H01L2924/00

摘要： An electrical interconnect structure on a substrate, which includes: a first low-k dielectric layer; a spin-on low k CMP protective layer that is covalently bonded to the first low-k dielectric layer; and a CVD deposited hardmask/CMP polish stop layer is provided. Electrical vias and lines can be formed in the first low k dielectric layer. The spin-on low k CMP protective layer prevents damage to the low k dielectric which can be created due to non-uniformity in the CMP process from center to edge or in areas of varying metal density. The thickness of the low-k CMP protective layer can be adjusted to accommodate larger variations in the CMP process without significantly impacting the effective dielectric constant of the structure.

摘要翻译： 在基板上的电互连结构，其包括：第一低k电介质层; 共价键合到第一低k电介质层的自旋低k CMP保护层; 并提供CVD沉积的硬掩模/ CMP抛光停止层。 可以在第一低k电介质层中形成电通孔和线。 旋转低k CMP保护层可防止由于中心到边缘或不同金属密度区域的CMP工艺中的不均匀性而导致的低k电介质的损坏。 可以调节低k CMP保护层的厚度以适应CMP工艺中的较大变化，而不显着影响结构的有效介电常数。

公开(公告)号：USD372950S

公开(公告)日：1996-08-20

申请号：US40446

申请日：1995-06-19

申请人： Lee Nicholson

设计人： Lee Nicholson