公开(公告)号：US08324622B2

公开(公告)日：2012-12-04

申请号：US12651332

申请日：2009-12-31

申请人： John H. Zhang ,  Laertis Economikos ,  Robin Van Den Nieuwenhuizen ,  Wei-Tsu Tseng

发明人： John H. Zhang ,  Laertis Economikos ,  Robin Van Den Nieuwenhuizen ,  Wei-Tsu Tseng

IPC分类号： H01L23/58 ,  H01L29/10

CPC分类号： H01L22/20 ,  H01L22/14 ,  H01L24/05 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00

摘要： A method that includes forming a first level of active circuitry on a substrate, forming a first probe pad electrically connected to the first level of active circuitry where the first probe pad having a first surface, contacting the first probe pad with a probe tip that displaces a portion of the first probe pad above the first surface, and performing a chemical mechanical polish on the first probe pad to planarize the portion of the first probe pad above the first surface. The method also includes forming a second level of active circuitry overlying the first probe pad, forming a second probe pad electrically connected to the second level of active circuitry, contacting the second probe pad with a probe tip that displaces a portion of the probe pad, and chemically mechanically polishing the second probe pad to remove the portion displaced.

摘要翻译： 一种方法，其包括在衬底上形成第一电平的有源电路，形成电连接到所述第一电平有源电路的第一探针焊盘，其中所述第一探针焊盘具有第一表面，所述第一探针焊盘与所述第一探针焊盘接触， 所述第一探针焊盘的位于所述第一表面上方的部分，以及在所述第一探针焊盘上执行化学机械抛光，以在所述第一表面上方平坦化所述第一探针焊盘的所述部分。 该方法还包括形成覆盖在第一探针焊盘上的第二电平有源电路，形成电连接到第二电平有源电路的第二探针焊盘，使第二探针焊盘与移位探针焊盘的一部分的探针尖接触， 以及化学机械地抛光第二探针垫以除去所移动的部分。

公开(公告)号：US20070287367A1

公开(公告)日：2007-12-13

申请号：US11422753

申请日：2006-06-07

申请人： Ben Kim ,  Manoj Balachandran ,  James Aloysius Hagan ,  Deoram Persaud ,  Adam Daniel Ticknor ,  Wei-tsu Tseng

发明人： Ben Kim ,  Manoj Balachandran ,  James Aloysius Hagan ,  Deoram Persaud ,  Adam Daniel Ticknor ,  Wei-tsu Tseng

IPC分类号： B24D11/00

CPC分类号： B24B53/017 ,  B24B53/12

摘要： The present invention is an apparatus and method for extending the life of abrasive disks used in the conditioning of polishing pads used in chemical mechanical planarization (CMP) of polishing pads used to polish and/or planarize the surfaces of semiconductor wafers during the production of integrated circuits. The invention consists of the a disk comprising a plurality of abrasive segments, each of which is fixed in tangential and radial relationship to one another about the common axis of rotation of the conditioning disk. Means are provided for movement of the abrasive segments, individually or in sets, into or out of the plane of the active abrasive surface of the conditioning disk according to the present invention.

摘要翻译： 本发明是一种用于延长研磨盘的寿命的装置和方法，用于在用于在生产集成的半导体晶片的表面中抛光和/或平面化半导体晶片的表面的抛光垫的化学机械平面化（CMP）中使用的抛光垫 电路。 本发明由包括多个磨料段的盘组成，每个研磨段围绕调节盘的公共旋转轴线彼此以切向和径向关系固定。 根据本发明，提供了用于将研磨段单独地或组合地移动到调节盘的活性研磨表面的平面内或外的装置。

公开(公告)号：US20050023689A1

公开(公告)日：2005-02-03

申请号：US10628925

申请日：2003-07-28

申请人： Lee Nicholson ,  Wei-Tsu Tseng ,  Christy Tyberg

发明人： Lee Nicholson ,  Wei-Tsu Tseng ,  Christy Tyberg

IPC分类号： H01L21/283 ,  H01L21/304 ,  H01L21/31 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48

CPC分类号： H01L23/5329 ,  H01L21/76807 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/7684 ,  H01L21/7688 ,  H01L2924/0002 ,  Y10T428/31663 ,  H01L2924/00

摘要： An electrical interconnect structure on a substrate, which includes: a first low-k dielectric layer; a spin-on low k CMP protective layer that is covalently bonded to the first low-k dielectric layer; and a CVD deposited hardmask/CMP polish stop layer is provided. Electrical vias and lines can be formed in the first low k dielectric layer. The spin-on low k CMP protective layer prevents damage to the low k dielectric which can be created due to non-uniformity in the CMP process from center to edge or in areas of varying metal density. The thickness of the low-k CMP protective layer can be adjusted to accommodate larger variations in the CMP process without significantly impacting the effective dielectric constant of the structure.

摘要翻译： 在基板上的电互连结构，其包括：第一低k电介质层; 共价键合到第一低k电介质层的自旋低k CMP保护层; 并提供CVD沉积的硬掩模/ CMP抛光停止层。 可以在第一低k电介质层中形成电通孔和线。 旋转低k CMP保护层可防止由于中心到边缘或不同金属密度区域的CMP工艺中的不均匀性而导致的低k电介质的损坏。 可以调节低k CMP保护层的厚度以适应CMP工艺中的较大变化，而不显着影响结构的有效介电常数。

公开(公告)号：US06660820B1

公开(公告)日：2003-12-09

申请号：US10205278

申请日：2002-07-24

申请人： Arthur Martin ,  Wei-Tsu Tseng

发明人： Arthur Martin ,  Wei-Tsu Tseng

IPC分类号： C08F13616

CPC分类号： C08F36/20 ,  C08F38/00

摘要： A new class of fluorinated arylacetylene compounds useful as monomers in the formation of polymers having low dielectric constant. These polymers, which are the reaction products of one of the fluorinated arylacetylene compounds, a diphenyl oxide biscyclopentadienone and, optionally, 1,3,5-tris(phenylacetylene)benzene, are useful in insulating microelectric device.

摘要翻译： 一类新的氟代芳基乙炔化合物，可用作形成具有低介电常数的聚合物的单体。 这些聚合物是氟化芳基乙炔化合物之一，二苯基氧基双环戊二烯酮和任选的1,3,5-三（苯基乙炔）苯的反应产物，可用于绝缘微电子器件。

公开(公告)号：US06441465B2

公开(公告)日：2002-08-27

申请号：US09246924

申请日：1999-02-09

申请人： Chi-Fa Lin ,  Wei-Tsu Tseng ,  Min-Shinn Feng

发明人： Chi-Fa Lin ,  Wei-Tsu Tseng ,  Min-Shinn Feng

IPC分类号： H01L23544

CPC分类号： H01L22/32 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A scribe line structure of a semiconductor wafer is provided in the invention. The semiconductor wafer has a plurality of substantially parallel horizontal scribe lines and a plurality of substantially parallel vertical scribe lines to separate a plurality of chips from each other. According to the invention, each parallel horizontal scribe line and each parallel vertical scribe line are divided along two elongated sides thereof into a plurality of portions with the same rectangular area. Each of the plurality of portions of each scribe line is composed of the scribe line structure. The scribe line structure comprises a multi-layer structure with four sides formed over whole area of each portion of each scribe line and at least two rows of cavities formed along the four sides of the multi-layer structure. The cavities of the scribe line structure are capable of relieving internal stress of the scribe lines and arresting possible cracks induced during scribe line manufacture. Thereby, peeling, delamination and dielectric fracture of the scribe lines induced during the wafer manufacture can be prevented.

摘要翻译： 在本发明中提供半导体晶片的划线结构。 半导体晶片具有多个基本上平行的水平划线和多个基本上平行的垂直划线以将多个芯片彼此分开。 根据本发明，每个平行的水平划线和每个平行的垂直划线沿其两个细长边划分成具有相同矩形区域的多个部分。 每个划线的多个部分中的每一个由划线结构组成。 划线结构包括多层结构，在每个划线的每个部分的整个区域上形成四边，并且沿多层结构的四边形成至少两排空腔。 划痕线结构的空腔能够减轻划痕线的内部应力，并阻止在划线生产过程中引起的可能的裂纹。 由此，能够防止在晶片制造时引起的划线的剥离，分层和介电断裂。

公开(公告)号：US06235608B1

公开(公告)日：2001-05-22

申请号：US09292772

申请日：1999-04-14

申请人： Chi-Fa Lin ,  Wei-Tsu Tseng ,  Min-Shinn Feng

发明人： Chi-Fa Lin ,  Wei-Tsu Tseng ,  Min-Shinn Feng

IPC分类号： H01L21336

CPC分类号： H01L21/31144 ,  H01L21/31053 ,  H01L21/31612 ,  H01L21/3185 ,  H01L21/76224 ,  Y10S438/97

摘要： A process for forming shallow trench isolation (STI) structures. It includes the steps of: (a) depositing a composite silicon nitride on to the silicon substrate; (b) forming a shallow trench on the silicon substrate by etching, using the composite silicon nitride as the hard mask; (c) depositing a filler oxide layer inside the shallow trench as well as on top of the composite silicon nitride, using a chemical vapor deposition (CVD) method; and (d) using a chemical-mechanical polishing (CMP) process to planarize the filler oxide layer using the composite nitride as a CMP stop. The composite silicon nitride comprises a plurality of silicon nitride layers whose CMP removal rate increases with the distance from the silicon substrate. Additionally, a composite silicon oxide layer can be formed on top of the filler oxide layer which comprises a plurality of silicon oxide layers whose CMP removal rate increases with the distance from the silicon substrate.

摘要翻译： 一种用于形成浅沟槽隔离（STI）结构的工艺。 它包括以下步骤：（a）将复合氮化硅沉积到硅衬底上; （b）使用复合氮化硅作为硬掩模，通过蚀刻在硅衬底上形成浅沟槽; （c）使用化学气相沉积（CVD）方法在浅沟槽内以及在复合氮化硅的顶部上沉积填充氧化物层; 和（d）使用化学机械抛光（CMP）工艺来使用复合氮化物作为CMP停止层来平坦化填充氧化物层。 复合氮化硅包括多个氮化硅层，其CMP去除率随着与硅衬底的距离而增加。 此外，可以在填充氧化物层的顶部上形成复合氧化硅层，其包括多个氧化硅层，其CMP去除速率随着与硅衬底的距离而增加。

公开(公告)号：US20130063173A1

公开(公告)日：2013-03-14

申请号：US13615368

申请日：2012-09-13

申请人： John H. Zhang ,  Laertis Economikos ,  Robin Van Den Nieuwenhuizen ,  Wei-Tsu Tseng

发明人： John H. Zhang ,  Laertis Economikos ,  Robin Van Den Nieuwenhuizen ,  Wei-Tsu Tseng

IPC分类号： G01R1/04

CPC分类号： H01L22/20 ,  H01L22/14 ,  H01L24/05 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00

摘要： A method that includes forming a first level of active circuitry on a substrate, forming a first probe pad electrically connected to the first level of active circuitry where the first probe pad having a first surface, contacting the first probe pad with a probe tip that displaces a portion of the first probe pad above the first surface, and performing a chemical mechanical polish on the first probe pad to planarize the portion of the first probe pad above the first surface. The method also includes forming a second level of active circuitry overlying the first probe pad, forming a second probe pad electrically connected to the second level of active circuitry, contacting the second probe pad with a probe tip that displaces a portion of the probe pad, and chemically mechanically polishing the second probe pad to remove the portion displaced.

摘要翻译： 一种方法，其包括在衬底上形成第一电平的有源电路，形成电连接到所述第一电平有源电路的第一探针焊盘，其中所述第一探针焊盘具有第一表面，所述第一探针焊盘与所述第一探针焊盘接触， 所述第一探针焊盘的位于所述第一表面上方的部分，以及在所述第一探针焊盘上执行化学机械抛光，以在所述第一表面上方平坦化所述第一探针焊盘的所述部分。 该方法还包括形成覆盖在第一探针焊盘上的第二电平有源电路，形成电连接到第二电平有源电路的第二探针焊盘，使第二探针焊盘与移位探针焊盘的一部分的探针尖接触， 以及化学机械地抛光第二探针垫以除去所移动的部分。

公开(公告)号：US20110156032A1

公开(公告)日：2011-06-30

申请号：US12651332

申请日：2009-12-31

申请人： John H. Zhang ,  Laertis Economikos ,  Robin Van Den Nieuwenhuizen ,  Wei-Tsu Tseng

发明人： John H. Zhang ,  Laertis Economikos ,  Robin Van Den Nieuwenhuizen ,  Wei-Tsu Tseng

IPC分类号： H01L23/485 ,  H01L21/768

CPC分类号： H01L22/20 ,  H01L22/14 ,  H01L24/05 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00

摘要： A method that includes forming a first level of active circuitry on a substrate, forming a first probe pad electrically connected to the first level of active circuitry where the first probe pad having a first surface, contacting the first probe pad with a probe tip that displaces a portion of the first probe pad above the first surface, and performing a chemical mechanical polish on the first probe pad to planarize the portion of the first probe pad above the first surface. The method also includes forming a second level of active circuitry overlying the first probe pad, forming a second probe pad electrically connected to the second level of active circuitry, contacting the second probe pad with a probe tip that displaces a portion of the probe pad, and chemically mechanically polishing the second probe pad to remove the portion displaced.

摘要翻译： 一种方法，其包括在衬底上形成第一电平的有源电路，形成电连接到所述第一电平有源电路的第一探针焊盘，其中所述第一探针焊盘具有第一表面，所述第一探针焊盘与所述第一探针焊盘接触， 所述第一探针焊盘的位于所述第一表面上方的部分，以及在所述第一探针焊盘上执行化学机械抛光，以在所述第一表面上方平坦化所述第一探针焊盘的所述部分。 该方法还包括形成覆盖在第一探针焊盘上的第二电平有源电路，形成电连接到第二电平有源电路的第二探针焊盘，使第二探针焊盘与移位探针焊盘的一部分的探针尖接触， 以及化学机械地抛光第二探针垫以除去所移动的部分。

公开(公告)号：US07253098B2

公开(公告)日：2007-08-07

申请号：US10711145

申请日：2004-08-27

申请人： Shyng-Tsong T. Chen ,  Kaushik Arun Kumar ,  Stephen Edward Greco ,  Shom Ponoth ,  Terry Allen Spooner ,  David L. Rath ,  Wei-Tsu Tseng

发明人： Shyng-Tsong T. Chen ,  Kaushik Arun Kumar ,  Stephen Edward Greco ,  Shom Ponoth ,  Terry Allen Spooner ,  David L. Rath ,  Wei-Tsu Tseng

IPC分类号： H01L21/4763

CPC分类号： H01L21/7684 ,  H01L21/3212 ,  H01L21/76832 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A chemical mechanical polishing (CMP) step is used to remove excess conductive material (e.g., Cu) overlying a low-k or ultralow-k interlevel dielectric layer (ILD) layer having trenches filled with conductive material, for a damascene interconnect structure. A reactive ion etch (RIE) or a Gas Cluster Ion Beam (GCIB) process is used to remove a portion of a liner which is atop a hard mask. A wet etch step is used to remove an oxide portion of the hard mask overlying the ILD, followed by a final touch-up Cu CMP (CMP) step which chops the protruding Cu patterns off and lands on the SiCOH hard mask. In this manner, processes used to remove excess conductive material substantially do not affect the portion of the hard mask overlying the interlevel dielectric layer.

摘要翻译： 化学机械抛光（CMP）步骤用于去除覆盖在具有填充有导电材料的沟槽的低k或超低k层间介质层（ILD）层上的过剩导电材料（例如Cu），用于镶嵌互连结构。 使用反应离子蚀刻（RIE）或气体簇离子束（GCIB）方法去除位于硬掩模顶部的衬垫的一部分。 使用湿蚀刻步骤去除覆盖在ILD上的硬掩模的氧化物部分，随后是最后的上覆Cu CMP（CMP）步骤，其将突出的Cu图案切掉并落在SiCOH硬掩模上。 以这种方式，用于去除过量的导电材料的工艺基本上不影响覆盖层间电介质层的硬掩模的部分。

公开(公告)号：US20060166012A1

公开(公告)日：2006-07-27

申请号：US11369476

申请日：2006-03-07

申请人： Lee Nicholson ,  Wei-Tsu Tseng ,  Christy Tyberg

发明人： Lee Nicholson ,  Wei-Tsu Tseng ,  Christy Tyberg

IPC分类号： B32B9/04

CPC分类号： H01L23/5329 ,  H01L21/76807 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/7684 ,  H01L21/7688 ,  H01L2924/0002 ,  Y10T428/31663 ,  H01L2924/00

摘要： An electrical interconnect structure on a substrate, which includes: a first low-k dielectric layer; a spin-on low k CMP protective layer that is covalently bonded to the first low-k dielectric layer; and a CVD deposited hardmask/CMP polish stop layer is provided. Electrical vias and lines can be formed in the first low k dielectric layer. The spin-on low k CMP protective layer prevents damage to the low k dielectric which can be created due to non-uniformity in the CMP process from center to edge or in areas of varying metal density. The thickness of the low-k CMP protective layer can be adjusted to accommodate larger variations in the CMP process without significantly impacting the effective dielectric constant of the structure.

摘要翻译： 在基板上的电互连结构，其包括：第一低k电介质层; 共价键合到第一低k电介质层的自旋低k CMP保护层; 并提供CVD沉积的硬掩模/ CMP抛光停止层。 可以在第一低k电介质层中形成电通孔和线。 旋转低k CMP保护层可防止由于中心到边缘或不同金属密度区域的CMP工艺中的不均匀性而导致的低k电介质的损坏。 可以调节低k CMP保护层的厚度以适应CMP工艺中的较大变化，而不显着影响结构的有效介电常数。