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    SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING
    3.
    发明申请
    SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING 有权
    半导体结构及其制造方法

    公开(公告)号：US20130043590A1

    公开(公告)日：2013-02-21

    申请号：US13212469

    申请日：2011-08-18

    Applicant: Mei-Hsuan LIN ,  Chih-Hsun LIN ,  Chih-Kang CHAO ,  Ling-Sung WANG

    Inventor： Mei-Hsuan LIN ,  Chih-Hsun LIN ,  Chih-Kang CHAO ,  Ling-Sung WANG

    IPC: H01L21/768 ,  H01L23/48

    CPC classification number: H01L23/481 ,  H01L21/76802 ,  H01L21/76822 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present application discloses a method of manufacturing a semiconductor structure. According to at least one embodiment, a first etch stop layer is formed over a conductive feature and a substrate, and the conductive feature is positioned over the substrate. A second etch stop layer is formed over the first etch stop layer. A first etch is performed to form an opening in the second etch stop layer, and the opening exposes a portion of the first etch stop layer. A second etch is performed to extend the opening downwardly by removing a portion of the exposed first etch stop layer, and the extended opening exposes a portion of the conductive feature.

    Abstract translation: 本申请公开了一种制造半导体结构的方法。 根据至少一个实施例，在导电特征和衬底之上形成第一蚀刻停止层，并且导电特征位于衬底上。 在第一蚀刻停止层上形成第二蚀刻停止层。 执行第一蚀刻以在第二蚀刻停止层中形成开口，并且开口暴露第一蚀刻停止层的一部分。 执行第二蚀刻以通过去除暴露的第一蚀刻停止层的一部分向下延伸开口，并且延伸的开口暴露导电特征的一部分。

    Method and system for modifying doped region design layout during mask preparation to tune device performance
    7.
    发明授权
    Method and system for modifying doped region design layout during mask preparation to tune device performance 有权
    在掩模准备期间修改掺杂区域设计布局以调整器件性能的方法和系统

    公开(公告)号：US08527915B2

    公开(公告)日：2013-09-03

    申请号：US13286410

    申请日：2011-11-01

    Applicant: Mei-Hsuan Lin ,  Ling-Sung Wang ,  Chih-Hsun Lin ,  Chih-Kang Chao

    Inventor： Mei-Hsuan Lin ,  Ling-Sung Wang ,  Chih-Hsun Lin ,  Chih-Kang Chao

    IPC: G06F17/50

    CPC classification number: G06F17/5068 ,  H01L21/26586 ,  H01L29/6659

    Abstract: The present disclosure provides a method and system for modifying a doped region design layout during mask preparation to tune device performance. An exemplary method includes receiving an integrated circuit design layout designed to define an integrated circuit, wherein the integrated circuit design layout includes a doped feature layout; identifying an area of the integrated circuit for device performance modification, and modifying a portion of the doped feature layout that corresponds with the identified area of the integrated circuit during a mask preparation process, thereby providing a modified doped feature layout.

    Abstract translation: 本公开提供了一种用于在掩模准备期间修改掺杂区域设计布局以调谐设备性能的方法和系统。 一种示例性方法包括接收设计成定义集成电路的集成电路设计布局，其中集成电路设计布局包括掺杂特征布局; 识别用于器件性能修改的集成电路的区域，以及在掩模准备过程期间修改与所识别的集成电路的区域相对应的掺杂特征布局的一部分，从而提供修改的掺杂特征布局。

    Method of manufacturing a semiconductor device
    8.
    发明授权
    Method of manufacturing a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US08470660B2

    公开(公告)日：2013-06-25

    申请号：US13234296

    申请日：2011-09-16

    Applicant: Mei-Hsuan Lin ,  Chih-Kang Chao ,  Chih-Hsun Lin ,  Ling-Sung Wang

    Inventor： Mei-Hsuan Lin ,  Chih-Kang Chao ,  Chih-Hsun Lin ,  Ling-Sung Wang

    IPC: H01L21/8238

    CPC classification number: H01L21/8238 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/66636 ,  H01L29/7848

    Abstract: A method of manufacturing a semiconductor device is disclosed. The exemplary method includes providing a substrate having a source region and a drain region. The method further includes forming a first recess in the substrate within the source region and a second recess in the substrate within the drain region. The first recess has a first plurality of surfaces and the second recess has a second plurality of surfaces. The method also includes epi-growing a semiconductor material in the first and second recesses and, thereafter, forming shallow isolation (STI) features in the substrate.

    Abstract translation: 公开了制造半导体器件的方法。 该示例性方法包括提供具有源极区和漏极区的衬底。 该方法还包括在源极区域内的衬底中形成第一凹槽，以及在漏极区域内的衬底中形成第二凹部。 第一凹部具有第一多个表面，第二凹部具有第二多个表面。 该方法还包括在第一和第二凹陷中外延生长半导体材料，然后在衬底中形成浅隔离（STI）特征。

    Method of Manufacturing a Semiconductor Device
    9.
    发明申请
    Method of Manufacturing a Semiconductor Device 有权
    制造半导体器件的方法

    公开(公告)号：US20130071995A1

    公开(公告)日：2013-03-21

    申请号：US13234296

    申请日：2011-09-16

    Applicant: Mei-Hsuan Lin ,  Chih-Kang Chao ,  Chih-Hsun Lin ,  Ling-Sung Wang

    Inventor： Mei-Hsuan Lin ,  Chih-Kang Chao ,  Chih-Hsun Lin ,  Ling-Sung Wang

    IPC: H01L21/762 ,  H01L21/76

    CPC classification number: H01L21/8238 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/66636 ,  H01L29/7848

    Abstract: A method of manufacturing a semiconductor device is disclosed. The exemplary method includes providing a substrate having a source region and a drain region. The method further includes forming a first recess in the substrate within the source region and a second recess in the substrate within the drain region. The first recess has a first plurality of surfaces and the second recess has a second plurality of surfaces. The method also includes epi-growing a semiconductor material in the first and second recesses and, thereafter, forming shallow isolation (STI) features in the substrate.

    Abstract translation: 公开了制造半导体器件的方法。 该示例性方法包括提供具有源极区和漏极区的衬底。 该方法还包括在源极区域内的衬底中形成第一凹槽，以及在漏极区域内的衬底中形成第二凹部。 第一凹部具有第一多个表面，第二凹部具有第二多个表面。 该方法还包括在第一和第二凹陷中外延生长半导体材料，然后在衬底中形成浅隔离（STI）特征。

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