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    Systems for Characterizing Resonance Behavior of Magnetostrictive Resonators
    1.
    发明申请
    Systems for Characterizing Resonance Behavior of Magnetostrictive Resonators 有权
    用于表征磁致伸缩谐振器谐振特性的系统

    公开(公告)号：US20120280682A1

    公开(公告)日：2012-11-08

    申请号：US13441572

    申请日：2012-04-06

    申请人： Zhongyang Cheng ,  Anxue Zhang ,  Kewei Zhang ,  Bryan Chin

    发明人： Zhongyang Cheng ,  Anxue Zhang ,  Kewei Zhang ,  Bryan Chin

    IPC分类号： G01R33/341 ,  G01R33/46

    CPC分类号： G01N29/2412 ,  G01N29/30 ,  G01N33/02 ,  G01N2291/014 ,  G01N2291/023 ,  G01R33/44

    摘要： Illustrative embodiments of systems for characterizing resonance behavior of magnetostrictive resonators are disclosed. In one illustrative embodiment, an apparatus may comprise a first channel including one or more driving coils and one or more magnetostrictive resonators, the first channel having a first impedance; a second channel having a second impedance, the second impedance differing from the first impedance by an impedance attributable to the one or more magnetostrictive resonators; a signal source configured to apply an input signal to both the first and second channels; and a signal receiver configured to generate a combined output signal in response to output signals measured from both the first and second channels.

    摘要翻译： 公开了用于表征磁致伸缩谐振器的谐振特性的系统的说明性实施例。 在一个说明性实施例中，装置可以包括包括一个或多个驱动线圈和一个或多个磁致伸缩谐振器的第一通道，第一通道具有第一阻抗; 具有第二阻抗的第二通道，所述第二阻抗与所述第一阻抗不同，所述阻抗可归因于所述一个或多个磁致伸缩谐振器; 信号源，被配置为向第一和第二通道施加输入信号; 以及信号接收器，被配置为响应于从第一和第二通道测量的输出信号产生组合的输出信号。

    Fast invalidation for cache coherency in distributed shared memory system
    2.
    发明授权
    Fast invalidation for cache coherency in distributed shared memory system 有权
    分布式共享内存系统中缓存一致性的快速无效

    公开(公告)号：US07613882B1

    公开(公告)日：2009-11-03

    申请号：US11668275

    申请日：2007-01-29

    申请人： Isam Akkawi ,  Michael Woodacre ,  Bryan Chin ,  Krishnan Subramani ,  Najeeb Imran Ansari ,  Chetana Nagendra Keltcher ,  Janakiramanan Vaidyanathan

    发明人： Isam Akkawi ,  Michael Woodacre ,  Bryan Chin ,  Krishnan Subramani ,  Najeeb Imran Ansari ,  Chetana Nagendra Keltcher ,  Janakiramanan Vaidyanathan

    IPC分类号： G06F12/08 ,  G06F15/163

    CPC分类号： G06F12/0833

    摘要： An example embodiment of the present invention provides processes relating to a cache coherence protocol for distributed shared memory. In one process, a DSM-management chip receives a request to modify a block of memory stored on a node that includes the chip and one or more CPUs, which request is marked for fast invalidation and comes from one of the CPUs. The DSM-management chip sends probes, also marked for fast invalidation, to DSM-management chips on other nodes where the block of memory is cached and responds to the original probe, allowing the requested modification to proceed without waiting for responses from the probes. Then the DSM-management chip delays for a pre-determined time period before incrementing the value of a serial counter which operates in connection with another serial counter to prevent data from leaving the node's CPUs over the network until responses to the probes have been received.

    摘要翻译： 本发明的示例性实施例提供了与分布式共享存储器的高速缓存一致性协议有关的处理。 在一个过程中，DSM管理芯片接收修改存储在包括芯片的节点和一个或多个CPU的存储器块的请求，该请求被标记为快速无效，并且来自其中一个CPU。 DSM管理芯片还将标记为快速无效的探针发送到存储器块缓存的其他节点上的DSM管理芯片，并对原始探针进行响应，从而允许请求的修改进行，而无需等待探测器的响应。 然后，DSM管理芯片在增加与另一个串行计数器连接的串行计数器的值之前延迟预定时间段，以防止数据通过网络离开节点的CPU，直到已经接收到对探针的响应。

    QoS based dynamic execution engine selection
    6.
    发明授权
    QoS based dynamic execution engine selection 有权
    基于QoS的动态执行引擎选择

    公开(公告)号：US09129060B2

    公开(公告)日：2015-09-08

    申请号：US13272975

    申请日：2011-10-13

    申请人： Najeeb I. Ansari ,  Michael Carns ,  Jeffrey Schroeder ,  Bryan Chin

    发明人： Najeeb I. Ansari ,  Michael Carns ,  Jeffrey Schroeder ,  Bryan Chin

    IPC分类号： G06F9/50 ,  G06F13/362

    CPC分类号： G06F9/30181 ,  G06F9/30 ,  G06F9/30145 ,  G06F9/38 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/50 ,  G06F9/5044 ,  G06F13/362

    摘要： In one embodiment, a processor includes plural processing cores, and plural instruction stores, each instruction store storing at least one instruction, each instruction having a corresponding group number, each instruction store having a unique identifier. The processor also includes a group execution matrix having a plurality of group execution masks and a store execution matrix comprising a plurality of store execution masks. The processor further includes a core selection unit that, for each instruction within each instruction store, selects a store execution mask from the store execution matrix. The core selection unit for each instruction within each instruction store selects at least one group execution mask from the group execution matrix. The core selection unit performs logic operations to create a core request mask. The processor includes an arbitration unit that determines instruction priority among each instruction, assigns an instruction for each available core, and signals the instruction store.

    摘要翻译： 在一个实施例中，处理器包括多个处理核心和多个指令存储器，每个指令存储器存储至少一个指令，每个指令具有对应的组号，每个指令存储器具有唯一的标识符。 处理器还包括具有多个组执行掩码的组执行矩阵和包括多个存储执行掩码的存储执行矩阵。 处理器还包括核心选择单元，对于每个指令存储器中的每个指令，从存储执行矩阵中选择存储执行掩码。 每个指令存储器中的每个指令的核心选择单元从组执行矩阵中选择至少一个组执行掩码。 核心选择单元执行逻辑操作以创建核心请求掩码。 处理器包括确定每个指令之间的指令优先级的仲裁单元，为每个可用的核心分配指令，并向指令存储器发出信号。

    Block Caching for Cache-Coherent Distributed Shared Memory
    7.
    发明申请
    Block Caching for Cache-Coherent Distributed Shared Memory 审中-公开
    缓存相干分布式共享内存的块缓存

    公开(公告)号：US20110004729A1

    公开(公告)日：2011-01-06

    申请号：US11959758

    申请日：2007-12-19

    申请人： Isam Akkawi ,  Najeeb Imran Ansari ,  Bryan Chin ,  Chetana Nagendra Keltcher ,  Krishnan Subramani ,  Janakiramanan Vaidyanathan

    发明人： Isam Akkawi ,  Najeeb Imran Ansari ,  Bryan Chin ,  Chetana Nagendra Keltcher ,  Krishnan Subramani ,  Janakiramanan Vaidyanathan

    IPC分类号： G06F12/08

    CPC分类号： G06F12/082 ,  G06F12/0813

    摘要： Methods, apparatuses, and systems directed to the caching of blocks of lines of memory in a cache-coherent, distributed shared memory system. Block caches used in conjunction with line caches can be used to store more data with less tag memory space compared to the use of line caches alone and can therefore reduce memory requirements. In one particular embodiment, the present invention manages this caching using a DSM-management chip, after the allocation of the blocks by software, such as a hypervisor. An example embodiment provides processing relating to block caches in cache-coherent distributed shared memory.

    摘要翻译： 针对缓存相干，分布式共享存储器系统中缓存存储器块的方法，装置和系统。 与线路高​​速缓存结合使用的块高速缓存可以与单独使用线路高速缓存相比，用于存储具有较少标签存储空间的更多数据，因此可以减少内存需求。 在一个特定实施例中，本发明在通过诸如管理程序的软件分配块之后，使用DSM管理芯片来管理该缓存。 示例性实施例提供了与高速缓存一致分布式共享存储器中的块高速缓存相关的处理。

    Method and System for Community Data Caching
    9.
    发明申请
    Method and System for Community Data Caching 有权
    社区数据缓存的方法和系统

    公开(公告)号：US20060190607A1

    公开(公告)日：2006-08-24

    申请号：US11379985

    申请日：2006-04-24

    申请人： Keith Lowery ,  Bryan Chin ,  David Consolver ,  Gregg DeMasters

    发明人： Keith Lowery ,  Bryan Chin ,  David Consolver ,  Gregg DeMasters

    IPC分类号： G06F15/173

    CPC分类号： H04L67/1063 ,  G06F17/30902 ,  H04L67/1046 ,  H04L67/1048 ,  H04L67/1051 ,  H04L67/2814 ,  H04L67/289 ,  Y10S707/99932

    摘要： A cache module (26) at a client computer (12) controls a cache portion (28) on a storage device (24). The cache module communicates with other cache modules at other clients to form a cache community (15). The cache modules store World Wide Web or other content in the cache portions for retrieval in response to requests (32) for content from browsers (30) in the cache community. When the requested content is not available in the cache community, the requested content may be retrieved from an origin server (19) using the Internet.

    摘要翻译： 在客户计算机（12）处的高速缓存模块（26）控制存储设备（24）上的高速缓存部分（28）。 缓存模块与其他客户端上的其他缓存模块进行通信，形成缓存区（15）。 缓存模块存储万维网或高速缓存部分中的其他内容以响应来自缓存区域中的浏览器（30）的内​​容的请求（32）来检索。 当请求的内容在缓存社区中不可用时，可以使用因特网从原始服务器（19）检索所请求的内容。

    Magnetostrictive ligand sensor
    10.
    发明申请
    Magnetostrictive ligand sensor 有权
    磁致伸缩配体传感器

    公开(公告)号：US20050074904A1

    公开(公告)日：2005-04-07

    申请号：US10923414

    申请日：2004-08-20

    申请人： Bryan Chin ,  Zhongyang Cheng ,  Vitaly Vodyanoy ,  James Barbaree ,  Valery Petrenko ,  Tung-Shi Huang ,  Howard Wikle

    发明人： Bryan Chin ,  Zhongyang Cheng ,  Vitaly Vodyanoy ,  James Barbaree ,  Valery Petrenko ,  Tung-Shi Huang ,  Howard Wikle

    IPC分类号： G01N33/543 ,  G01N33/553

    CPC分类号： G01N27/745 ,  G01N33/5434

    摘要： A magnetostrictive ligand sensor device (MLSD), system and method are provided having at least one magnetostrictive particle (MSP) to which is bound at least one binding element. The MSP may be dispersed in a sample containing a target ligand such that the target ligand binds thereto. A driver is also provided to emit a varying magnetic field such that the MSP produces a resonance response detectable by a measurement device configured to receive and detect changes in the resonance response that are due to alterations of the binding element. The MLSD and assays find use in identifying and quantitating ligands as well as chemicals and environmental conditions in a sample or patient.

    摘要翻译： 提供了具有至少一个磁致伸缩颗粒（MSP）的磁致伸缩配体传感器装置（MLSD），系统和方法，其结合至少一个结合元件。 MSP可以分散在含有靶配体的样品中，使得靶配体与其结合。 还提供驱动器以发射变化的磁场，使得MSP产生由测量装置可检测的共振响应，该测量装置被配置为接收和检测由于绑定元件的改变而引起的共振响应的变化。 MLSD和测定法用于鉴定和定量配体以及样品或患者中的化学物质和环境条件。