公开(公告)号：US08933537B2

公开(公告)日：2015-01-13

申请号：US12998869

申请日：2009-12-03

申请人： Alexander Fox ,  Bernd Heinemann ,  Steffen Marschmeyer

发明人： Alexander Fox ,  Bernd Heinemann ,  Steffen Marschmeyer

IPC分类号： H01L27/102 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/161 ,  H01L29/732 ,  H01L29/737

CPC分类号： H01L29/66242 ,  H01L21/8222 ,  H01L21/8249 ,  H01L29/0804 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/7371

摘要： A semiconductor device, comprising a substrate layer made of a semiconductor material of a first conductivity type and having a first insulation region, and a vertical bipolar transistor having a first vertical portion of a collector made of monocrystalline semiconductor material of a second conductivity type and disposed in an opening of the first insulation region, a second insulation region lying partly on the first vertical portion of the collector and partly on the first insulation region and having an opening in the region of the collector, in which opening a second vertical portion of the collector made of monocrystalline material is disposed, said portion including an inner region of the second conductivity type, a base made of monocrystalline semiconductor material of the first conductivity type, a base connection region surrounding the base in the lateral direction, a T-shaped emitter made of semiconductor material of the second conductivity type and overlapping the base connection region, wherein the base connection region, aside from a seeding layer adjacent the substrate or a metallization layer adjacent a base contact, consists of a semiconductor material which differs in its chemical composition from the semiconductor material of the collector, the base and the emitter and in which the majority charge carriers of the first conductivity type have greater mobility compared thereto.

摘要翻译： 一种半导体器件，包括由第一导电类型的半导体材料制成并具有第一绝缘区域的衬底层和垂直双极晶体管，其具有由第二导电类型的单晶半导体材料制成的集电体的第一垂直部分，并且被布置 在第一绝缘区域的开口中，第二绝缘区域部分地位于集电器的第一垂直部分上并且部分地位于第一绝缘区域上并且在集电器的区域中具有开口，其中开口的第二垂直部分 设置由单晶材料构成的集电体，所述部分包括第二导电类型的内部区域，由第一导电类型的单晶半导体材料制成的基底，在横向方向上围绕基底的基极连接区域，T形发射极 由第二导电类型的半导体材料制成并与基底连接重叠 其中基底连接区域除了与基底相邻的晶种层或邻近基极接触处的金属化层组成，其半导体材料的化学成分不同于集电极，基极和发射极的半导体材料 并且其中第一导电类型的多数电荷载流子具有比其更大的迁移率。

公开(公告)号：US08546249B2

公开(公告)日：2013-10-01

申请号：US12449335

申请日：2008-02-15

申请人： Bernd Tillack ,  Bernd Heinemann ,  Yuji Yamamoto

发明人： Bernd Tillack ,  Bernd Heinemann ,  Yuji Yamamoto

IPC分类号： H01L29/04 ,  C23C16/24 ,  H01L33/16

CPC分类号： C23C16/24 ,  C23C16/0272 ,  C23C16/04 ,  C23C16/28 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/02639

摘要： A method of depositing polycrystalline silicon exclusively on monocrystalline first silicon surface portions of a substrate surface which besides the first surface portions additionally has insulator surface portions, comprising the steps of depositing boron on the first silicon surface portions in an amount which in relation to the first silicon surface portions respectively corresponds to more than a monolayer of boron, and depositing silicon on the first silicon surface portions treated in that way.

摘要翻译： 一种仅在基板表面的单晶第一硅表面部分上沉积多晶硅的方法，除了第一表面部分之外，还具有绝缘体表面部分，该方法包括以下步骤：在第一硅表面部分上沉积硼，其量相对于第一 硅表面部分分别对应于多于单层的硼，并且在以这种方式处理的第一硅表面部分上沉积硅。

公开(公告)号：US20090179303A1

公开(公告)日：2009-07-16

申请号：US11792015

申请日：2005-12-12

申请人： Bernd Heinemann ,  Holger Rücker ,  Jürgen Drews ,  Steffen Marschmayer

发明人： Bernd Heinemann ,  Holger Rücker ,  Jürgen Drews ,  Steffen Marschmayer

IPC分类号： H01L29/732 ,  H01L21/331

CPC分类号： H01L29/66287 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

摘要： A vertical heterobipolar transistor comprising a substrate of semiconductor material of a first conductivity type and an insulation region provided therein, a first semiconductor electrode arranged in an opening of the insulation region and comprising monocrystalline semiconductor material of a second conductivity type, which is either in the form of a collector or an emitter, and which has a first heightwise portion and an adjoining second heightwise portion which is further away from the substrate interior in a heightwise direction, wherein only the first heightwise portion is enclosed by the insulation region in lateral directions perpendicular to the heightwise direction, a second semiconductor electrode of semiconductor material of the second conductivity type, which is in the form of the other type of semiconductor electrode, a base of monocrystalline semiconductor material of the first conductivity type, and a base connection region having a monocrystalline portion which in a lateral direction laterally surrounds the second heightwise portion, which is further towards the substrate interior as viewed from the base, of the first semiconductor electrode, and which rests with its underside directly on the insulation region.

摘要翻译： 一种垂直异双极晶体管，包括第一导电类型的半导体材料的衬底和设置在其中的绝缘区域，布置在绝缘区域的开口中的第一半导体电极，并且包括第二导电类型的单晶半导体材料， 收集器或发射器的形式，并且具有第一高度部分和相邻的第二高度部分，其在高度方向上远离基板内部，其中只有第一高度方向部分被垂直的横向方向上的绝缘区域包围 第二导电类型的半导体材料的第二半导体电极是另一种类型的半导体电极的形式的第二半导体电极，第一导电类型的单晶半导体材料的基底和具有第一导电类型的基底连接区域 单晶部分 横向方向横向地围绕第二高度方向部分，第二高度方向部分从第一半导体电极的基部朝向基板内部，并且其下侧直接位于绝缘区域上。

公开(公告)号：US06800881B2

公开(公告)日：2004-10-05

申请号：US10234440

申请日：2002-08-30

申请人： Gunther Lippert ,  Hans-Jörg Osten ,  Bernd Heinemann

发明人： Gunther Lippert ,  Hans-Jörg Osten ,  Bernd Heinemann

IPC分类号： H01L31072

CPC分类号： H01L29/7378 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66242

摘要： A silicon-germanium hetero bipolar transistor comprising a silicon collector layer, a boron-doped silicon-germanium base layer, a silicon emitter layer and an emitter contact area. The transistor is fabricated using an epitaxy process on a surface of pure silicon. An electrically inert material is incorporated into the epitaxial layers in order to link the defects in the semiconductor structure and to reduce the outdiffusion of the dopant. Thus, a transistor for high-frequency applications can be fabricated in two ways: to increase the dopant dose of the base region or to reduce the thickness of the base layer. In particular, an implantation or doped region having a T-shaped cross section profile is provided between the emitter layer and the emitter contact area.

摘要翻译： 一种硅 - 锗异质双极晶体管，包括硅集电极层，硼掺杂硅 - 锗基底层，硅发射极层和发射极接触区域。 晶体管使用在纯硅表面上的外延工艺制造。 为了连接半导体结构中的缺陷并减少掺杂剂的扩散，将电惰性材料结合到外延层中。 因此，用于高频应用的晶体管可以以两种方式制造：增加基极区的掺杂剂剂量或减小基底层的厚度。 特别地，在发射极层和发射极接触区域之间提供具有T形横截面轮廓的注入或掺杂区域。

公开(公告)号：US08035167B2

公开(公告)日：2011-10-11

申请号：US12448032

申请日：2007-12-07

申请人： Dieter Knoll ,  Bernd Heinemann ,  Karl-Ernst Ehwald

发明人： Dieter Knoll ,  Bernd Heinemann ,  Karl-Ernst Ehwald

IPC分类号： H01L27/015

CPC分类号： H01L27/0623 ,  H01L21/82285 ,  H01L21/8249 ,  H01L27/0826

摘要： A complementary bipolar semiconductor device (CBi semiconductor device) comprising a substrate of a first conductivity type, active bipolar transistor regions in the substrate, in which the base, emitter and collector of vertical bipolar transistors are arranged, vertical epitaxial-base npn bipolar transistors in a first subset of the active bipolar transistor regions, vertical epitaxial-base pnp bipolar transistors in a second subset of the active bipolar transistor regions, collector contact regions which are respectively arranged adjoining an active bipolar transistor region, and shallow field insulation regions which respectively laterally delimit the active bipolar transistor regions and the collector contact regions, wherein arranged between the first or the second or both the first and also the second subset of active bipolar transistor regions on the one hand and the adjoining collector contact regions on the other hand is a respective shallow field insulation region of a first type with a first depthwise extent in the direction of the substrate interior and shallow field insulation regions of a second type of a second greater depthwise extent than the first depthwise extent of the active bipolar transistor regions delimit the active bipolar transistor regions and collector contact regions viewed in cross-section at their sides facing away from each other.

摘要翻译： 一种互补双极性半导体器件（CBi半导体器件），包括第一导电类型的衬底，衬底中的有源双极晶体管区域，其中垂直双极晶体管的基极，发射极和集电极被布置，垂直外延基极npn双极晶体管 有源双极晶体管区域的第一子集，有源双极晶体管区域的第二子集中的垂直外延基极pnp双极晶体管，分别布置成邻接有源双极晶体管区域的集电极接触区域和分别横向 界定有源双极性晶体管区域和集电极接触区域，其中一方面被布置在一方面的有源双极性晶体管区域的第一或第二或第二子集之间，另一方面相邻的集电极接触区域是 相应的浅场绝缘区域为第一 在基板内部的方向上具有第一深度方向的第一类型，并且第二类型的浅的场绝缘区域比有源双极晶体管区域的第一深度方向的第二较深的深度方向的区域限定有源双极晶体管区域和集电极接触区域 横截面在彼此背离的一侧。

公开(公告)号：US20100019326A1

公开(公告)日：2010-01-28

申请号：US12448032

申请日：2007-12-07

申请人： Dieter Knoll ,  Bernd Heinemann ,  Karl-Ernst Ehwald

发明人： Dieter Knoll ,  Bernd Heinemann ,  Karl-Ernst Ehwald

IPC分类号： H01L27/06 ,  H01L21/8249

CPC分类号： H01L27/0623 ,  H01L21/82285 ,  H01L21/8249 ,  H01L27/0826

摘要： A complementary bipolar semiconductor device (CBi semiconductor device) comprising a substrate of a first conductivity type, active bipolar transistor regions in the substrate, in which the base, emitter and collector of vertical bipolar transistors are arranged, vertical epitaxial-base npn bipolar transistors in a first subset of the active bipolar transistor regions, vertical epitaxial-base pnp bipolar transistors in a second subset of the active bipolar transistor regions, collector contact regions which are respectively arranged adjoining an active bipolar transistor region, and shallow field insulation regions which respectively laterally delimit the active bipolar transistor regions and the collector contact regions, wherein arranged between the first or the second or both the first and also the second subset of active bipolar transistor regions on the one hand and the adjoining collector contact regions on the other hand is a respective shallow field insulation region of a first type with a first depthwise extent in the direction of the substrate interior and shallow field insulation regions of a second type of a second greater depthwise extent than the first depthwise extent of the active bipolar transistor regions delimit the active bipolar transistor regions and collector contact regions viewed in cross-section at their sides facing away from each other.

摘要翻译： 一种互补双极性半导体器件（CBi半导体器件），包括第一导电类型的衬底，衬底中的有源双极晶体管区域，其中垂直双极晶体管的基极，发射极和集电极被布置，垂直外延基极npn双极晶体管 有源双极晶体管区域的第一子集，有源双极晶体管区域的第二子集中的垂直外延基极pnp双极晶体管，分别布置成邻接有源双极晶体管区域的集电极接触区域和分别横向 界定有源双极性晶体管区域和集电极接触区域，其中一方面被布置在一方面的有源双极性晶体管区域的第一或第二或第二子集之间，另一方面相邻的集电极接触区域是 相应的浅场绝缘区域为第一 在基板内部的方向上具有第一深度方向的第一类型，并且第二类型的第二类型的浅的场绝缘区域比有源双极性晶体管区域的第一深度方向的第二较深的深度方向的区域限定了观察到的有源双极晶体管区域和集电极接触区域 横截面在彼此背离的一侧。

公开(公告)号：US20070278621A1

公开(公告)日：2007-12-06

申请号：US10580669

申请日：2004-12-03

申请人： Holger Rucker ,  Bernd Heinemann

发明人： Holger Rucker ,  Bernd Heinemann

IPC分类号： H01L29/70 ,  H01L21/331

CPC分类号： H01L29/66287 ,  H01L29/0649 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

摘要： A bipolar transistor has a base with an epitaxial base layer and a raised base connection region which in a lateral direction in parallel relationship with the substrate surface encloses the emitter which is surrounded by a spacer of insulating material. The epitaxial base layer is raised in a heightwise direction perpendicularly to the substrate surface. An emitter of a T-shaped cross-sectional profile is separated laterally from the outer base portion by a spacer of insulating material. Its vertical bar of the T-shape adjoins with its lower end the inner base portion. The lateral extent of the spacer increases from its interface with respect to the base layer with increasing height above the base layer, wherein a first interface formed by the emitter and the spacer meets a second interface formed by the emitter and the inner base portion at a first angle which is either a right angle or an obtuse angle, and a third interface formed by the spacer and the outer base portion meets the second interface at a second obtuse angle which is larger than the first angle.

摘要翻译： 双极晶体管具有基底，其具有外延基底层和凸起的基底连接区域，该基底连接区域在与衬底表面平行的方向上包围由绝缘材料的隔离物围绕的发射器。 外延基层在与基板表面垂直的高度方向上升高。 通过绝缘材料的间隔件将T形横截面轮廓的发射器从外部基部侧向分开。 其T形的垂直杆的下端与内部基部相邻。 间隔物的横向范围从其相对于基底层的界面增加，其高度高于基底层，其中由发射体和间隔物形成的第一界面与由发射体和内部基底部分形成的第二界面在 第一角度是直角或钝角，并且由间隔件和外基部形成的第三界面以大于第一角度的第二钝角与第二界面相交。

公开(公告)号：US06465318B1

公开(公告)日：2002-10-15

申请号：US09787571

申请日：2001-08-02

申请人： Karl-Ernst Ehwald ,  Bernd Tillack ,  Bernd Heinemann ,  Dieter Knoll ,  Dirk Wolansky

发明人： Karl-Ernst Ehwald ,  Bernd Tillack ,  Bernd Heinemann ,  Dieter Knoll ,  Dirk Wolansky

IPC分类号： H01L21331

CPC分类号： H01L29/66287 ,  H01L29/7322

摘要： This invention relates to a bi-polar transistor and a procedure for its manufacture. The task of the invention is to propose a bi-polar transistor and a procedure for its manufacture that eliminates the disadvantages of conventional arrangements for a simple polysilicon technology with differential epitaxy for the manufacture of the base, in order to further improve especially the high-speed properties of a bi-polar transistor, to produce highly conductive connections between the metal contacts and the active (inner) transistor region as well as a minimized passive transistor surface, and to simultaneously avoid any additional process complexity and increased contact resistance. This invention resolves the task in that, by creating suitable epitaxy process conditions, the polysilicon layer is deposited on the insulator zone with a greater thickness than the epitaxy layer in the active transistor zone. The greater thickness of the polysilicon layer as compared to the epitaxial layer is achieved by using a very low temperature for the deposition of a part of or the entire buffer layer. The use of a low temperature for the deposition allows a better nucleation of the insulator layer and a reduction of the idle time for the deposition. This allows achieving a greater thickness on the insulator layer as compared with the active transistor zone.

摘要翻译： 本发明涉及双极晶体管及其制造方法。 本发明的任务是提出一种双极晶体管及其制造方法，其消除了用于制造基底的具有差分外延的简单多晶硅技术的常规布置的缺点， 双极晶体管的速度特性，以在金属触点和有源（内部）晶体管区域之间产生高导电连接以及最小化的无源晶体管表面，同时避免任何额外的工艺复杂性和增加的接触电阻。 本发明解决了通过创建合适的外延工艺条件的工作，多晶硅层以比有源晶体管区中的外延层更大的厚度沉积在绝缘体区上。 与外延层相比，多晶硅层的厚度越大，通过使用非常低的温度来沉积一部分或整个缓冲层来实现。 使用低温进行沉积允许绝缘体层的更好的成核和减少沉积的空闲时间。 与有源晶体管区域相比，这允许在绝缘体层上实现更大的厚度。

公开(公告)号：US20090206335A1

公开(公告)日：2009-08-20

申请号：US10581127

申请日：2004-12-01

申请人： Bernd Heinemann ,  Jürgen Drews ,  Steffen Marschmayer ,  Holger Rücker

发明人： Bernd Heinemann ,  Jürgen Drews ,  Steffen Marschmayer ,  Holger Rücker

IPC分类号： H01L27/082 ,  H01L29/04 ,  H01L21/8228 ,  H01L21/782

CPC分类号： H01L21/82285 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0826

摘要： The invention relates to a BiCMOS device comprising a substrate having a first type of conductivity and a number of active regions that are provided therein and are delimited in a lateral direction by flat field-insulating regions. Vertical npn bipolar epitaxial base transistors are disposed in a first partial number of the active regions while vertical pnp bipolar epitaxial base transistors are arranged in a second partial number of the active regions of the BiCMOS device. One transistor type or both transistor types are provided with both a collector region and a collector contact region in one and the same respective active region. In order to improve the high frequency characteristics, an insulation doping region that is configured so as to electrically insulate the collector and the substrate is provided between the collector region and the substrate exclusively in a first transistor type in which the type of conductivity of the substrate corresponds to that of the collector region. In addition, the collector region of the first transistor type or both transistor types is laterally delimited by the flat field-insulating regions.

摘要翻译： 本发明涉及一种BiCMOS器件，其包括具有第一类型的导电性的衬底和设置在其中的多个有源区，并且通过平坦的场绝缘区在横向方向上界定。 垂直npn双极外延基极晶体管被布置在第一部分数量的有源区中，而垂直pnp双极外延基极晶体管被布置在BiCMOS器件的有效区的第二部分数目中。 一个晶体管类型或两个晶体管类型在同一个相同的有源区域中设置有集电极区域和集电极接触区域。 为了提高高频特性，仅在集电极区域和衬底之间设置用于使集电极和衬底电绝缘的绝缘掺杂区域仅以基板的导电性类型的第一晶体管类型提供 对应于集电极区域。 此外，第一晶体管类型或两种晶体管类型的集电极区域由平坦的场绝缘区域横向界定。

公开(公告)号：US06878995B2

公开(公告)日：2005-04-12

申请号：US10239933

申请日：2001-03-24

申请人： Karl-Ernst Ehwald ,  Bernd Heinemann ,  Dieter Knoll ,  Wolfgang Winkler

发明人： Karl-Ernst Ehwald ,  Bernd Heinemann ,  Dieter Knoll ,  Wolfgang Winkler

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L21/335

CPC分类号： H01L29/66659 ,  H01L29/0615 ,  H01L29/1033 ,  H01L29/7835

摘要： A CMOS-compatible DMOS transistor can be designed by virtue of a suitable layout configuration optionally for very high drain voltages or for power amplification at very high frequencies and which can be produced at a low level of additional cost in comparison with a conventional sub-μm production technology for CMOS circuits. A gate insulator of the transistor is of a unitary thickness under a control gate in the entire (active) region through which current flows. A zone of increased doping concentration (well region) which is near the surface and which determines the transistor threshold voltage is so arranged under the control gate that it occupies the entire area under the control gate which is on the active region and ends within a so-called drift space between the control gate and a highly doped drain region. The entire surface of the drift space is covered by a zone of the conductivity type of the drain region (VLDD), which is lowly doped in comparison with the highly doped drain region.

摘要翻译： 可以通过适当的布局配置来设计CMOS兼容的DMOS晶体管，用于非常高的漏极电压或在非常高的频率下进行功率放大，并且可以以与常规子母线相比低的额外成本来生产CMOS兼容的DMOS晶体管 CMOS电路的生产技术。 在电流流过的整个（有源）区域中，晶体管的栅极绝缘体在控制栅极下方具有整体厚度。 靠近表面并确定晶体管阈值电压的增加的掺杂浓度（阱区）的区域被布置在控制栅极下方，其占据位于有源区上的控制栅极下方的整个区域并且结束于其中 在控制栅极和高掺杂漏极区之间的偏移漂移空间。 漂移空间的整个表面由漏区（VLDD）的导电类型的区域覆盖，其与高掺杂漏极区相比被低掺杂。