摘要:
This invention relates to a bi-polar transistor and a procedure for its manufacture. The task of the invention is to propose a bi-polar transistor and a procedure for its manufacture that eliminates the disadvantages of conventional arrangements for a simple polysilicon technology with differential epitaxy for the manufacture of the base, in order to further improve especially the high-speed properties of a bi-polar transistor, to produce highly conductive connections between the metal contacts and the active (inner) transistor region as well as a minimized passive transistor surface, and to simultaneously avoid any additional process complexity and increased contact resistance. This invention resolves the task in that, by creating suitable epitaxy process conditions, the polysilicon layer is deposited on the insulator zone with a greater thickness than the epitaxy layer in the active transistor zone. The greater thickness of the polysilicon layer as compared to the epitaxial layer is achieved by using a very low temperature for the deposition of a part of or the entire buffer layer. The use of a low temperature for the deposition allows a better nucleation of the insulator layer and a reduction of the idle time for the deposition. This allows achieving a greater thickness on the insulator layer as compared with the active transistor zone.
摘要:
The invention relates to layers in substrate wafers. The aim of the invention is to provide layers in substrate wafers with which the drawbacks of conventional assemblies are overcome in order to achieve, on the one hand, an adequate resistance to latch-up in highly scaled, digital CMOS circuits with comparatively low costs and, on the other hand, to ensure low substrate losses/couplings for analog high-frequency circuits and, in addition, to influence the component behavior in a non-destructive manner. To these ends, the invention provides that in a highly resistive p-Si substrate (2) with one or more buried high-carbon Si layers (3) under an epitaxial layer and with the Si cap layer (4), an implantation dose, which is greater in comparison to conventional substrate wafers, is used for retrograde trough profiles by suppressing the dopant diffusion as well as the generation of defects when remedying implant defects, thereby achieving a reduction of the trough resistance, and finally, an increase in the resistance to latch-up.
摘要:
System for producing diffusion-inhibiting epitaxial semiconductor layers, by means of which thin diffusion-inhibiting, epitaxial semiconductor layers can be produced on large semiconductor substrates at a high throughput.The surfaces of the semiconductor substrates to be coated are first cleaned, and the substrates are then heated in a low pressure batch reactor to a first temperature (prebake temperature). The surfaces to be coated are next subjected to a hydrogen prebake operation at a first reactor pressure. In the next step the semiconductor substrates are heated in a low pressure hot or warm wall batch reactor to a second temperature (deposition temperature) lower than the first temperature, and after a condition of thermodynamic equilibrium is reached the diffusion-inhibiting semiconductor layers are deposited on the surfaces to be coated in a chemical gaseous deposition process (CVD) at a second reactor pressure higher than, equal to or lower than the first reactor pressure.