公开(公告)号：US06465318B1

公开(公告)日：2002-10-15

申请号：US09787571

申请日：2001-08-02

申请人： Karl-Ernst Ehwald ,  Bernd Tillack ,  Bernd Heinemann ,  Dieter Knoll ,  Dirk Wolansky

发明人： Karl-Ernst Ehwald ,  Bernd Tillack ,  Bernd Heinemann ,  Dieter Knoll ,  Dirk Wolansky

IPC分类号： H01L21331

CPC分类号： H01L29/66287 ,  H01L29/7322

摘要： This invention relates to a bi-polar transistor and a procedure for its manufacture. The task of the invention is to propose a bi-polar transistor and a procedure for its manufacture that eliminates the disadvantages of conventional arrangements for a simple polysilicon technology with differential epitaxy for the manufacture of the base, in order to further improve especially the high-speed properties of a bi-polar transistor, to produce highly conductive connections between the metal contacts and the active (inner) transistor region as well as a minimized passive transistor surface, and to simultaneously avoid any additional process complexity and increased contact resistance. This invention resolves the task in that, by creating suitable epitaxy process conditions, the polysilicon layer is deposited on the insulator zone with a greater thickness than the epitaxy layer in the active transistor zone. The greater thickness of the polysilicon layer as compared to the epitaxial layer is achieved by using a very low temperature for the deposition of a part of or the entire buffer layer. The use of a low temperature for the deposition allows a better nucleation of the insulator layer and a reduction of the idle time for the deposition. This allows achieving a greater thickness on the insulator layer as compared with the active transistor zone.

摘要翻译： 本发明涉及双极晶体管及其制造方法。 本发明的任务是提出一种双极晶体管及其制造方法，其消除了用于制造基底的具有差分外延的简单多晶硅技术的常规布置的缺点， 双极晶体管的速度特性，以在金属触点和有源（内部）晶体管区域之间产生高导电连接以及最小化的无源晶体管表面，同时避免任何额外的工艺复杂性和增加的接触电阻。 本发明解决了通过创建合适的外延工艺条件的工作，多晶硅层以比有源晶体管区中的外延层更大的厚度沉积在绝缘体区上。 与外延层相比，多晶硅层的厚度越大，通过使用非常低的温度来沉积一部分或整个缓冲层来实现。 使用低温进行沉积允许绝缘体层的更好的成核和减少沉积的空闲时间。 与有源晶体管区域相比，这允许在绝缘体层上实现更大的厚度。

公开(公告)号：US07595534B2

公开(公告)日：2009-09-29

申请号：US10433969

申请日：2001-12-06

申请人： Bernd Heinemann ,  Karl-Ernst Ehwald ,  Dieter Knoll ,  Bernd Tillack ,  Dirk Wolansky ,  Peter Schley

发明人： Bernd Heinemann ,  Karl-Ernst Ehwald ,  Dieter Knoll ,  Bernd Tillack ,  Dirk Wolansky ,  Peter Schley

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L21/74 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/1083

摘要： The invention relates to layers in substrate wafers. The aim of the invention is to provide layers in substrate wafers with which the drawbacks of conventional assemblies are overcome in order to achieve, on the one hand, an adequate resistance to latch-up in highly scaled, digital CMOS circuits with comparatively low costs and, on the other hand, to ensure low substrate losses/couplings for analog high-frequency circuits and, in addition, to influence the component behavior in a non-destructive manner. To these ends, the invention provides that in a highly resistive p-Si substrate (2) with one or more buried high-carbon Si layers (3) under an epitaxial layer and with the Si cap layer (4), an implantation dose, which is greater in comparison to conventional substrate wafers, is used for retrograde trough profiles by suppressing the dopant diffusion as well as the generation of defects when remedying implant defects, thereby achieving a reduction of the trough resistance, and finally, an increase in the resistance to latch-up.

摘要翻译： 本发明涉及衬底晶片中的层。 本发明的目的是提供衬底晶片中的层，其中克服了常规组件的缺点，以便一方面实现具有相对较低成本的高度缩放的数字CMOS电路中的闩锁的适当电阻，以及 另一方面，为了确保模拟高频电路的低衬底损耗/耦合，此外，以非破坏性的方式影响组件行为。 为此，本发明提供了在具有一个或多个掩埋的高碳Si层（3）的外延层和Si覆盖层（4）下的高电阻p-Si衬底（2）中的注入剂量， 与传统的基板晶片相比，通过抑制掺杂剂扩散以及在补偿注入缺陷时产生缺陷而用于逆向槽型材，从而实现了谷电阻的降低，最后增加了电阻 闭锁

公开(公告)号：US07244667B2

公开(公告)日：2007-07-17

申请号：US10484975

申请日：2002-07-25

申请人： Bernd Tillack ,  Dirk Wolansky ,  Georg Ritter ,  Thomas Grabolla

发明人： Bernd Tillack ,  Dirk Wolansky ,  Georg Ritter ,  Thomas Grabolla

IPC分类号： H01L21/205

CPC分类号： H01L21/02529 ,  C23C16/0218 ,  C23C16/54 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658

摘要： System for producing diffusion-inhibiting epitaxial semiconductor layers, by means of which thin diffusion-inhibiting, epitaxial semiconductor layers can be produced on large semiconductor substrates at a high throughput.The surfaces of the semiconductor substrates to be coated are first cleaned, and the substrates are then heated in a low pressure batch reactor to a first temperature (prebake temperature). The surfaces to be coated are next subjected to a hydrogen prebake operation at a first reactor pressure. In the next step the semiconductor substrates are heated in a low pressure hot or warm wall batch reactor to a second temperature (deposition temperature) lower than the first temperature, and after a condition of thermodynamic equilibrium is reached the diffusion-inhibiting semiconductor layers are deposited on the surfaces to be coated in a chemical gaseous deposition process (CVD) at a second reactor pressure higher than, equal to or lower than the first reactor pressure.

摘要翻译： 用于制造扩散抑制外延半导体层的系统，通过该系统，可以在大的半导体衬底上以高通量产生薄的扩散抑制性外延半导体层。 首先清洁待涂覆的半导体衬底的表面，然后将衬底在低压间歇反应器中加热到第一温度（预烘烤温度）。 待涂覆的表面接下来在第一反应器压力下进行氢预烘烤操作。 在下一步骤中，将半导体衬底在低压热或温壁间歇反应器中加热到低于第一温度的第二温度（沉积温度），并且在达到热力学平衡条件之后，沉积扩散抑制半导体层 在高于等于或低于第一反应器压力的第二反应器压力下在化学气相沉积工艺（CVD）中待涂覆的表面上。