公开(公告)号：US20130132683A1

公开(公告)日：2013-05-23

申请号：US13713614

申请日：2012-12-13

申请人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David J. Harriman ,  Mark B. Rosenbluth ,  Ajay V. Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert G. Blankenship ,  Ohad Falik ,  Avi Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

发明人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David J. Harriman ,  Mark B. Rosenbluth ,  Ajay V. Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert G. Blankenship ,  Ohad Falik ,  Avi Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC分类号： G06F12/08

CPC分类号： G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

摘要： A method and apparatus forenhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

公开(公告)号：US08397241B2

公开(公告)日：2013-03-12

申请号：US12317854

申请日：2008-12-30

申请人： Zhou Xiaocheng ,  Shoumeng Yan ,  Ying Gao ,  Hu Chen ,  Peinan Zhang ,  Mohan Rajagopalan ,  Avi Mendelson ,  Bratin Saha

发明人： Zhou Xiaocheng ,  Shoumeng Yan ,  Ying Gao ,  Hu Chen ,  Peinan Zhang ,  Mohan Rajagopalan ,  Avi Mendelson ,  Bratin Saha

IPC分类号： G06F9/44 ,  G06F13/14 ,  G06F13/00

CPC分类号： G06F9/544 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/1009 ,  G06F12/1063 ,  G06F12/1072 ,  G06F12/1081 ,  G06F12/109 ,  G06F2212/161 ,  G06F2212/622 ,  G06F2212/656 ,  G06F2212/657 ,  G06F2212/682 ,  G06T1/20 ,  G06T1/60

摘要： Embodiments of the invention provide language support for CPU-GPU platforms. In one embodiment, code can be flexibly executed on both the CPU and GPU. CPU code can offload a kernel to the GPU. That kernel may in turn call preexisting libraries on the CPU, or make other calls into CPU functions. This allows an application to be built without requiring the entire call chain to be recompiled. Additionally, in one embodiment data may be shared seamlessly between CPU and GPU. This includes sharing objects that may have virtual functions. Embodiments thus ensure the right virtual function gets invoked on the CPU or the GPU if a virtual function is called by either the CPU or GPU.

公开(公告)号：US20070150703A1

公开(公告)日：2007-06-28

申请号：US11301058

申请日：2005-12-12

申请人： Avi Mendelson ,  Michael Mishaeli ,  Julius Mandelblat

发明人： Avi Mendelson ,  Michael Mishaeli ,  Julius Mandelblat

IPC分类号： G06F9/30

CPC分类号： G06F9/524

摘要： In one embodiment, the present invention includes a method including initiating a cleaning operation to clear a first processor core of a system of pending operations, and preventing injection of new events into a second processor core if the cleaning operation is not serviced in the first processor core. In this way, lock situations may be broken without their detection. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括一种方法，包括启动清理操作以清除待处理操作的系统的第一处理器核心，以及如果在第一处理器中没有服务于清洁操作，则防止将新事件注入到第二处理器核心 核心。 以这种方式，锁定情况可能在没有检测到的情况下被破坏。 描述和要求保护其他实施例。

公开(公告)号：US07141953B2

公开(公告)日：2006-11-28

申请号：US10934295

申请日：2004-09-03

申请人： Aviad Cohen ,  Lev Finkelstein ,  Avi Mendelson ,  Ronny Ronen ,  Dmitry Rudoy

发明人： Aviad Cohen ,  Lev Finkelstein ,  Avi Mendelson ,  Ronny Ronen ,  Dmitry Rudoy

IPC分类号： H02P21/00

CPC分类号： H02H6/005 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172 ,  Y10S388/934

摘要： Methods, apparatus, and articles of manufacture control a device or system that has an operational limit related to the rate or frequency of operation. The frequency of operation is controlled at a variable rate calculated to maximize the system or apparatus performance over a calculated period of time short enough that a controlling factor, such as power consumption, does not vary significantly during the period. Known system parameters, such as thermal resistance and capacitance of an integrated circuit (IC) and its package, and measured values, such as current junction temperature in an IC, are used to calculate a time-dependent frequency of operation for the upcoming time period that results in the best overall performance without exceeding the operational limit, such as the junction temperature.

公开(公告)号：US20140375662A1

公开(公告)日：2014-12-25

申请号：US14320985

申请日：2014-07-01

申请人： HU CHEN ,  YING GAO ,  XIAOCHENG ZHOU ,  SHOUMENG YAN ,  PEINAN ZHANG ,  MOHAN RAJAGOPALAN ,  JESSE FANG ,  AVI MENDELSON ,  Bratin Saha

发明人： HU CHEN ,  YING GAO ,  XIAOCHENG ZHOU ,  SHOUMENG YAN ,  PEINAN ZHANG ,  MOHAN RAJAGOPALAN ,  JESSE FANG ,  AVI MENDELSON ,  Bratin Saha

IPC分类号： G06F12/10 ,  G06F12/08 ,  G06T1/60

CPC分类号： G06F9/544 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/1009 ,  G06F12/1063 ,  G06F12/1072 ,  G06F12/1081 ,  G06F12/109 ,  G06F2212/161 ,  G06F2212/622 ,  G06F2212/656 ,  G06F2212/657 ,  G06F2212/682 ,  G06T1/20 ,  G06T1/60

摘要： Embodiments of the invention provide a programming model for CPU-GPU platforms. In particular, embodiments of the invention provide a uniform programming model for both integrated and discrete devices. The model also works uniformly for multiple GPU cards and hybrid GPU systems (discrete and integrated). This allows software vendors to write a single application stack and target it to all the different platforms. Additionally, embodiments of the invention provide a shared memory model between the CPU and GPU. Instead of sharing the entire virtual address space, only a part of the virtual address space needs to be shared. This allows efficient implementation in both discrete and integrated settings.

摘要翻译： 本发明的实施例提供了一种用于CPU-GPU平台的编程模型。 特别地，本发明的实施例为集成和分立设备提供统一的编程模型。 该模型还适用于多个GPU卡和混合GPU系统（分立和集成）。 这允许软件供应商编写单个应用程序堆栈并将其定位到所有不同的平台。 另外，本发明的实施例提供了CPU和GPU之间的共享存储器模型。 而不是共享整个虚拟地址空间，只需要共享虚拟地址空间的一部分。 这允许在离散和集成设置中有效实现。

公开(公告)号：US20100118041A1

公开(公告)日：2010-05-13

申请号：US12317853

申请日：2008-12-30

申请人： Hu Chen ,  Ying Gao ,  Zhou Xiaocheng ,  Shoumeng Yan ,  Peinan Zhang ,  Mohan Rajagopalan ,  Jesse Fang ,  Avi Mendelson ,  Bratin Saha

发明人： Hu Chen ,  Ying Gao ,  Zhou Xiaocheng ,  Shoumeng Yan ,  Peinan Zhang ,  Mohan Rajagopalan ,  Jesse Fang ,  Avi Mendelson ,  Bratin Saha

IPC分类号： G06F15/167

CPC分类号： G06F9/544 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/1009 ,  G06F12/1063 ,  G06F12/1072 ,  G06F12/1081 ,  G06F12/109 ,  G06F2212/161 ,  G06F2212/622 ,  G06F2212/656 ,  G06F2212/657 ,  G06F2212/682 ,  G06T1/20 ,  G06T1/60

摘要： Embodiments of the invention provide a programming model for CPU-GPU platforms. In particular, embodiments of the invention provide a uniform programming model for both integrated and discrete devices. The model also works uniformly for multiple GPU cards and hybrid GPU systems (discrete and integrated). This allows software vendors to write a single application stack and target it to all the different platforms. Additionally, embodiments of the invention provide a shared memory model between the CPU and GPU. Instead of sharing the entire virtual address space, only a part of the virtual address space needs to be shared. This allows efficient implementation in both discrete and integrated settings.

摘要翻译： 本发明的实施例提供了一种用于CPU-GPU平台的编程模型。 特别地，本发明的实施例为集成和分立设备提供统一的编程模型。 该模型还适用于多个GPU卡和混合GPU系统（分立和集成）。 这允许软件供应商编写单个应用程序堆栈并将其定位到所有不同的平台。 另外，本发明的实施例提供了CPU和GPU之间的共享存储器模型。 而不是共享整个虚拟地址空间，只需要共享虚拟地址空间的一部分。 这允许在离散和集成设置中有效实现。

公开(公告)号：US06473777B1

公开(公告)日：2002-10-29

申请号：US09183200

申请日：1998-10-30

申请人： Danny Hendler ,  Jonathan Levy ,  Avi Mendelson

发明人： Danny Hendler ,  Jonathan Levy ,  Avi Mendelson

IPC分类号： G06F1730

CPC分类号： G06F9/45516 ,  G06F9/3879 ,  G06F9/44589 ,  Y10S707/99957

摘要： A coprocessor performs an overhead function of a Java virtual machine executing in a main processor. The coprocessor includes memory access circuitry configured to access a memory also accessible by the host processor. Pointer receiving circuitry is configured to receive at least one pointer to data in the memory pertinent to the overhead function. Function performing circuitry is configured to perform the overhead function to operate on the data in the memory pointed to by the at least one pointer. Result passing circuitry configured to pass a result back to the main processor. For example, overhead functions that may be performed by the coprocessor include bytecode verification, just-in-time compiling and garbage collection.

摘要翻译： 协处理器执行在主处理器中执行的Java虚拟机的开销功能。 协处理器包括被配置为访问也可由主处理器访问的存储器的存储器访问电路。 指针接收电路被配置为接收至少一个指向与开销功能相关的存储器中的数据的指针。 功能执行电路被配置为执行开销函数以对由至少一个指针指向的存储器中的数据进行操作。 结果传递电路被配置为将结果传递回主处理器。 例如，可由协处理器执行的开销函数包括字节码验证，即时编译和垃圾收集。

公开(公告)号：US5996060A

公开(公告)日：1999-11-30

申请号：US936738

申请日：1997-09-25

申请人： Avi Mendelson ,  Freddy Gabbay

发明人： Avi Mendelson ,  Freddy Gabbay

IPC分类号： G06F9/38 ,  G06F9/00

CPC分类号： G06F9/383 ,  G06F9/3455 ,  G06F9/3834

摘要： A processor and associated memory device that includes a fetcher for fetching instructions stored in the memory device. Each instruction constitutes either a value generating instruction or a non-value generating instruction. The processor further including a decoder for decoding the instructions, an issue unit for routing decoded instructions to an execution unit. The processor further having a predictor being responsive to a first set of instructions, from among the value generating instructions, for predicting, with respect to each one instruction in said first set of instructions, a predicted value that is determined on the basis of a prediction criterion which includes: (i) a previous value generated by the instruction; and (ii) at a stride.

摘要翻译： 一种处理器和相关联的存储器设备，其包括用于取出存储在存储器件中的指令的读取器。 每个指令构成值生成指令或非值生成指令。 处理器还包括用于解码指令的解码器，用于将解码的指令路由到执行单元的发布单元。 所述处理器进一步具有响应来自所述值生成指令的第一组指令的预测器，用于相对于所述第一组指令中的每个指令预测基于预测确定的预测值 标准包括：（i）由指令产生的先前值; 和（ii）一步一步。

公开(公告)号：US10185566B2

公开(公告)日：2019-01-22

申请号：US13994142

申请日：2012-04-27

申请人： Alon Naveh ,  Yuval Yosef ,  Eliezer Weissmann ,  Anil Aggarwal ,  Efraim Rotem ,  Avi Mendelson ,  Ronny Ronen ,  Boris Ginzburg ,  Michael Mishaeli ,  Scott D. Hahn ,  David A. Koufaty ,  Ganapati Srinivasa ,  Guy Therien

发明人： Alon Naveh ,  Yuval Yosef ,  Eliezer Weissmann ,  Anil Aggarwal ,  Efraim Rotem ,  Avi Mendelson ,  Ronny Ronen ,  Boris Ginzburg ,  Michael Mishaeli ,  Scott D. Hahn ,  David A. Koufaty ,  Ganapati Srinivasa ,  Guy Therien

IPC分类号： G06F9/30 ,  G06F9/48 ,  G06F9/50

摘要： In one embodiment, the present invention includes a multicore processor having first and second cores to independently execute instructions, the first core visible to an operating system (OS) and the second core transparent to the OS and heterogeneous from the first core. A task controller, which may be included in or coupled to the multicore processor, can cause dynamic migration of a first process scheduled by the OS to the first core to the second core transparently to the OS. Other embodiments are described and claimed.

公开(公告)号：US20100217161A1

公开(公告)日：2010-08-26

申请号：US12379565

申请日：2009-02-25

申请人： Avi Shalgi ,  Avi Mendelson

发明人： Avi Shalgi ,  Avi Mendelson

IPC分类号： A61N7/00 ,  A61B6/00

CPC分类号： A61N7/00 ,  A61B5/6843 ,  A61B8/4245 ,  A61B8/4281 ,  A61B2017/00084 ,  A61B2090/373 ,  A61N2007/0008

摘要： A system for delivering ultrasonic focused energy, the system comprising a transducer unit for delivering the ultrasonic focused energy, the transducer unit comprising an interface medium adapted to contact at least a portion of a treatment region in a treatment area, and further comprising an electromagnetic (EM) radiating element adapted to transmit EM radiation towards the interface medium, wherein a reflection of the EM radiation from the interface medium is indicative of an extent of acoustic contact; and an energy processing unit adapted to send electrical energy to the transducer unit.

摘要翻译： 一种用于传送超声聚焦能量的系统，所述系统包括用于传送超声聚焦能量的换能器单元，所述换能器单元包括适于接触治疗区域中的治疗区域的至少一部分的界面介质，并且还包括电磁 EM）辐射元件，适于向接口介质传输EM辐射，其中来自界面介质的EM辐射的反射指示声学接触的程度; 以及适于向所述换能器单元发送电能的能量处理单元。