公开(公告)号：US09337164B2

公开(公告)日：2016-05-10

申请号：US14525855

申请日：2014-10-28

申请人： Freescale Semiconductor, Inc.

发明人： Rama I. Hegde

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L23/495 ,  H01L21/48

CPC分类号： H01L24/45 ,  H01L21/4821 ,  H01L21/4846 ,  H01L23/49548 ,  H01L23/49582 ,  H01L23/49586 ,  H01L24/32 ,  H01L24/43 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/43 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45573 ,  H01L2224/45647 ,  H01L2224/45666 ,  H01L2224/45681 ,  H01L2224/45687 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/013 ,  H01L2924/0104 ,  H01L2924/01072 ,  H01L2924/00012

摘要： A coating layer for use in copper integrated circuit interconnect and other conductive structures hinders and decreases oxide growth on surfaces of such conductive structures. The coating layer includes an amorphous copper containing layer deposited on a crystalline copper substrate, such as utilized for a lead frame and a bonding wire. Additional amorphous layers may be interposed between the amorphous copper containing layer and the copper substrate, such as an amorphous tantalum nitride layer and an amorphous titanium nitride layer.

摘要翻译： 用于铜集成电路互连和其它导电结构的涂层阻碍并减少这种导电结构表面上的氧化物生长。 涂层包括沉积在结晶铜基底上的非晶态含铜层，例如用于引线框架和接合线。 可以在非晶态含铜层和铜基板之间插入附加非晶层，例如非晶氮化钽层和无定形氮化钛层。

公开(公告)号：US09094001B2

公开(公告)日：2015-07-28

申请号：US13503862

申请日：2009-11-12

申请人： Anton Rozen ,  Dan Kuzmin ,  Michael Priel

发明人： Anton Rozen ,  Dan Kuzmin ,  Michael Priel

IPC分类号： G06F1/00 ,  H03K19/003 ,  G06F1/30 ,  G06F1/26 ,  G06F1/28

CPC分类号： H03K19/00346 ,  G06F1/26 ,  G06F1/28 ,  G06F1/305

摘要： An integrated circuit and a method. The integrated circuit includes an internal component having an output for providing a driven input signal; an output driver, connected to the internal component, for converting said driven input signal in an output signal; an output pad for outputting said output signal to a component outside the integrated circuit; a power grid configured to supply a supply voltage to the output driver; a controllable current consuming component connected to the power grid, said connectable current consuming component being controllable to consume current in accordance with a supply voltage change reduction pattern; a change detector connected to the internal component and the controllable current consuming component, for detecting a change in said driven input signal prior to said change resulting in a change in said output signal and to control said current consuming component to consume current in response to said detecting.

摘要翻译： 一种集成电路和方法。 集成电路包括具有用于提供驱动输入信号的输出的内部部件; 连接到内部组件的输出驱动器，用于在输出信号中转换所述驱动输入信号; 输出焊盘，用于将所述输出信号输出到集成电路外的部件; 配置为向输出驱动器提供电源电压的电网; 连接到电网的可控电流消耗部件，所述可连接电流消耗部件可控制以根据电源电压变化减小模式消耗电流; 连接到内部组件和可控电流消耗部件的变化检测器，用于在所述变化之前检测所述驱动输入信号的变化，导致所述输出信号的变化，并且响应于所述输入信号控制所述电流消耗部件消耗电流 检测。

公开(公告)号：US08464069B2

公开(公告)日：2013-06-11

申请号：US11671271

申请日：2007-02-05

申请人： Lawrence L. Case ,  Thomas Tkacik

发明人： Lawrence L. Case ,  Thomas Tkacik

IPC分类号： H04L9/14

CPC分类号： G06F12/1458

摘要： Embodiments include systems and methods for securely accessing data in the context of a data transaction. A system may include a memory block, within which a memory partition may be allocated to the data transaction. The memory partition includes a data storage block and at least one binding register. The system also includes platform entities and an access control block, which determines whether a particular platform entity may access data within the data storage block, and whether a particular platform entity may write binding information into a binding register. Access also may be granted or denied based on the current state of a state machine associated with the data transaction. The system also includes a cipher/binding function adapted to encrypt the data, using the binding information, for storage on an unsecured memory device, and to decrypting encrypted data, using the binding information, which is retrieved from the unsecured memory device.

摘要翻译： 实施例包括用于在数据事务的上下文中安全访问数据的系统和方法。 系统可以包括存储器块，在该存储器块内可以将存储器分区分配给数据事务。 存储器分区包括数据存储块和至少一个绑定寄存器。 该系统还包括平台实体和访问控制块，其确定特定平台实体是否可以访问数据存储块内的数据，以及特定平台实体是否可以将绑定信息写入绑定寄存器。 还可以基于与数据事务相关联的状态机的当前状态来授予或拒绝访问。 该系统还包括适于使用绑定信息加密数据，用于存储在不安全的存储器设备上的密码/绑定功能，以及使用从不安全的存储器件检索的绑定信息对加密的数据进行解密。

公开(公告)号：US20110221307A1

公开(公告)日：2011-09-15

申请号：US13128032

申请日：2009-11-25

申请人： Lianjun Liu ,  Sergio Pacheco ,  Francois Perruchot ,  Emmanuel Defay ,  Patrice Rey

发明人： Lianjun Liu ,  Sergio Pacheco ,  Francois Perruchot ,  Emmanuel Defay ,  Patrice Rey

IPC分类号： H01L41/04

CPC分类号： B81B3/0072 ,  B81B2201/032 ,  H01L41/0933 ,  H01L41/094

摘要： A micro or nano electromechanical transducer device formed on a semiconductor substrate comprises a movable structure which is arranged to be movable in response to actuation of an actuating structure. The movable structure comprises a mechanical structure having at least one mechanical layer having a first thermal response characteristic, at least one layer of the actuating structure having a second thermal response characteristic different to the first thermal response characteristic, and a thermal compensation structure having at least one thermal compensation layer. The thermal compensation layer is different to the at least one layer and is arranged to compensate a thermal effect produced by the mechanical layer and the at least one layer of the actuating structure such that the movement of the movable structure is substantially independent of variations in temperature.

摘要翻译： 形成在半导体衬底上的微型或纳米机电换能器装置包括可移动结构，其被布置成响应于致动结构的致动而是可移动的。 可移动结构包括具有至少一个具有第一热响应特性的机械层的机械结构，至少一层致动结构具有不同于第一热响应特性的第二热响应特性，以及至少具有至少 一个热补偿层。 热补偿层不同于至少一个层，并且被布置成补偿由机械层和致动结构的至少一个层产生的热效应，使得可移动结构的运动基本上与温度变化无关 。

公开(公告)号：US07627030B2

公开(公告)日：2009-12-01

申请号：US11198602

申请日：2005-08-05

申请人： Jie Su ,  Yong Wang

发明人： Jie Su ,  Yong Wang

IPC分类号： H03H7/30

CPC分类号： H04B1/1027

摘要： A controllable equalizer is arranged to be automatically and selectively disabled and is configured to operate in a frequency modulated (FM) radio receiver. The controllable equalizer includes an equalizer (115) that is configured to perform an equalization algorithm, e.g., CMA, that relies on a predetermined distribution for a received signal, where the received signal is available from the FM radio receiver and a spurious signal detector (123) that is configured to determine whether a spurious signal is present in the received signal and to disable the equalizer when the spurious signal is present. A method (300) of automatically and selectively disabling an equalizer operating in a frequency modulated (FM) radio receiver includes performing an equalization algorithm (307) on an FM received signal, the equalization algorithm relying on a predetermined distribution of the FM received signal, determining whether a spurious signal is present (309) in the FM received signal; and disabling the equalizer (317) when the spurious signal is present in the FM received signal.

摘要翻译： 可控均衡器被布置成自动和选择性地禁用并且被配置为在调频（FM）无线电接收机中操作。 可控均衡器包括均衡器（115），其被配置为执行均衡算法，例如CMA，其依赖于接收信号的预定分布，其中接收信号可从FM无线电接收机和伪信号检测器（ 123），其被配置为确定寄生信号是否存在于接收信号中，并且当寄生信号存在时禁止均衡器。 自动和选择性地禁用在调频（FM）无线电接收机中操作的均衡器的方法（300）包括对FM接收信号执行均衡算法（307），所述均衡算法依赖于FM接收信号的预定分布， 确定FM接收信号中是否存在杂散信号（309）; 以及当FM接收信号中存在杂散信号时禁止均衡器（317）。

公开(公告)号：US07236756B2

公开(公告)日：2007-06-26

申请号：US10319188

申请日：2002-12-13

申请人： Michael McGinn

发明人： Michael McGinn

IPC分类号： H04B1/18 ,  H04B1/06 ,  H04B7/00

CPC分类号： H04B1/0003 ,  H04B1/18 ,  H04B1/28 ,  H04B1/406

摘要： A front end tuning system includes a tuning signal generator. The tuning signal generator includes a digital-to-analog converter (DAC) to receive a pre-conditioned tuning signal at a reference input, to receive a digital value at a digital control input, and to produce a modified tuning signal based on the digital value and the pre-conditioned signal. Preconditioning the tuning-voltage allows a simple current type DAC to be can be used, rather than an 8-bit ladder type DAC used by some other front end tuners. Significant cost savings can be achieved because less memory is required to store the digital values supplied to the DACs, and set up times can be reduced. An adjustable temperature compensation circuit provides additional adaptability.

摘要翻译： 前端调谐系统包括调谐信号发生器。 调谐信号发生器包括数模转换器（DAC），用于在参考输入处接收预调节的调谐信号，以在数字控制输入端接收数字值，并产生基于数字信号的修改的调谐信号 值和预处理信号。 预调节电压允许使用简单的电流型DAC，而不是其他一些前端调谐器使用的8位梯形DAC。 可以实现显着的成本节省，因为需要更少的存储器来存储提供给DAC的数字值，并且可以减少设置时间。 可调温度补偿电路提供额外的适应性。

公开(公告)号：US06884685B2

公开(公告)日：2005-04-26

申请号：US10366777

申请日：2003-02-14

申请人： Tien Ying Luo ,  Ricardo Garcia ,  Hsing H. Tseng

发明人： Tien Ying Luo ,  Ricardo Garcia ,  Hsing H. Tseng

IPC分类号： C23C16/30 ,  C23C16/40 ,  H01L21/28 ,  H01L21/314 ,  H01L21/316 ,  H01L29/51 ,  H01L21/336

CPC分类号： H01L21/28185 ,  C23C16/308 ,  C23C16/40 ,  H01L21/02181 ,  H01L21/02271 ,  H01L21/02362 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/3141 ,  H01L21/3143 ,  H01L21/31604 ,  H01L21/3162 ,  H01L21/31645 ,  H01L29/517 ,  H01L29/518

摘要： A metal oxide high-k dielectric is deposited on a semiconductor wafer in a manner that reduces dangling bonds in the dielectric without significantly thickening interfacial oxide thickness. A metal oxide precursor and radical oxygen and/or radical nitrogen are co-flowed over the semiconductor wafer to form the high-k dielectric. The radicals bond to dangling bonds of the metal of the metal oxide during the deposition process that is performed at the regular deposition temperature of less than about 400 degrees Celsius. The radical oxygen and radical nitrogen do not require the higher temperatures generally required in an anneal in order to attach to the dangling bonds of the metal. Thus, a high temperature post deposition anneal, which tends to cause interfacial oxide growth, is not required. The dielectric is of higher quality than is typical because the dangling bonds are removed during deposition rather than after the dielectric has been deposited.

摘要翻译： 金属氧化物高k电介质沉积在半导体晶片上，以减少电介质中的悬挂键而不显着增加界面氧化物厚度。 金属氧化物前体和自由基氧和/或自由基氮共同流过半导体晶片以形成高k电介质。 在沉积过程中，基团键合到金属氧化物的金属的悬挂键，其在小于约400摄氏度的常规沉积温度下进行。 自由基氧和自由基氮不需要在退火中通常需要的较高温度以附着到金属的悬挂键上。 因此，不需要倾向于引起界面氧化物生长的高温后沉积退火。 电介质的质量比典型值高，因为在沉积期间移除悬挂键，而不是沉积电介质后。

公开(公告)号：US06877123B2

公开(公告)日：2005-04-05

申请号：US10025291

申请日：2001-12-19

申请人： Thomas K. Johnston ,  Frank Frederick

发明人： Thomas K. Johnston ,  Frank Frederick

IPC分类号： G01R31/317 ,  G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318552 ,  G01R31/31727

摘要： Embodiments of the present invention relate generally to scan clock waveform generation. One embodiment utilizes global and local circular shift registers to provide a series of shift/capture pulses at a manageable frequency for the tester and launch pulses that are phase shifted in order to provide for at-speed testing. Therefore, scan test patterns may be shifted in or out of state elements at lower frequencies as compared to the normal operating frequency of the integrated circuit being tested, while still allowing for at-speed testing. An alternate embodiment utilizes a circular shift register in combination with static storage devices and waveform generators to provide the shift/capture pulses and launch pulses. Embodiments of the present invention also allow for clock inversion where the clock and clock bar signals are dependent during normal mode and independent during scan test mode.

摘要翻译： 本发明的实施例一般涉及扫描时钟波形生成。 一个实施例使用全局和局部圆形移位寄存器来提供针对测试器的可管理频率的一系列移位/捕获脉冲和相移的启动脉冲，以便提供高速测试。 因此，与待测集成电路的正常工作频率相比，扫描测试图案可以以更低的频率移入或移出状态元件，同时仍允许进行高速测试。 替代实施例利用与静态存储设备和波形发生器组合的循环移位寄存器来提供移位/捕获脉冲和启动脉冲。 本发明的实施例还允许时钟反转，其中时钟和时钟条信号在正常模式期间是依赖的，并且在扫描测试模式期间是独立的。

公开(公告)号：US09312834B1

公开(公告)日：2016-04-12

申请号：US14591924

申请日：2015-01-08

申请人： Mohit Parnami ,  Gaurav Goyal

发明人： Mohit Parnami ,  Gaurav Goyal

IPC分类号： H03K3/356 ,  H03K3/3562

CPC分类号： H03K3/35625 ,  H03K3/012

摘要： An integrated circuit having reduced power consumption includes a clock-gating cell, a transistor and a flip-flop. The clock-gating cell receives a dynamic enable signal, generates a latched-enable signal and gates a clock signal provided to the flip-flop. The flip-flop includes first and second latches. The transistor receives an inverted latched-enable signal from the clock-gating cell and switches ON or OFF based on the logic state of the inverted latched-enable signal. The transistor provides a voltage signal to the flip-flop circuit based on the state of the flip-flop in order to control the state of the flip-flop, which reduces power consumption of the integrated circuit.

摘要翻译： 具有降低功耗的集成电路包括时钟门控单元，晶体管和触发器。 时钟门控单元接收动态使能信号，产生锁存使能信号并门控提供给触发器的时钟信号。 触发器包括第一和第二锁存器。 晶体管从时钟门控单元接收反向锁存使能信号，并根据反相锁存使能信号的逻辑状态接通或断开。 晶体管基于触发器的状态向触发器电路提供电压信号，以便控制触发器的状态，这降低了集成电路的功耗。

公开(公告)号：US09002694B2

公开(公告)日：2015-04-07

申请号：US13463034

申请日：2012-05-03

申请人： Xiushan Feng ,  Jayanta Bhadra ,  Scott R. Little

发明人： Xiushan Feng ,  Jayanta Bhadra ,  Scott R. Little

IPC分类号： G06F17/50 ,  G06F1/32

CPC分类号： G06F17/5036 ,  G06F1/3203 ,  G06F17/5022 ,  G06F2217/78

摘要： An approach is provided in which a power design verification system retrieves a power intent data corresponding to a power design, which identifies the power design's power modes and power mode transition conditions. The power design verification system selects one of the power mode transition conditions, which identifies input signals that invoke a transition from a first power mode to a second power mode. In turn, the power design verification system generates simulation stimuli based upon the identified input signals and simulates the power design utilizing the generated simulation stimuli accordingly.

摘要翻译： 提供了一种方法，其中功率设计验证系统检索对应于功率设计的功率意图数据，其识别功率设计的功率模式和功率模式转换条件。 功率设计验证系统选择功率模式转换条件之一，其识别调用从第一功率模式到第二功率模式的转换的输入信号。 反过来，功率设计验证系统基于所识别的输入信号产生模拟刺激，并且相应地利用所产生的仿真刺激来模拟功率设计。