公开(公告)号：US20050156180A1

公开(公告)日：2005-07-21

申请号：US11065085

申请日：2005-02-24

Applicant: Zhibo Zhang ,  Veena Misra ,  Salah Bedair ,  Mehmet Ozturk

Inventor： Zhibo Zhang ,  Veena Misra ,  Salah Bedair ,  Mehmet Ozturk

IPC: H01L21/20 ,  H01L29/06 ,  H01L29/12 ,  H01L27/15 ,  H01L31/0328 ,  H01L33/00

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/02395 ,  H01L21/02463 ,  H01L21/02488 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/02642 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/125 ,  H01L29/127 ,  Y10S977/762

Abstract: Methods of forming a nano-scale electronic and optoelectronic devices include forming a substrate having a semiconductor layer therein and a substrate insulating layer on the semiconductor layer. An etching template having a first array of non-photolithographically defined nano-channels extending therethrough, is formed on the substrate insulating layer. This etching template may comprise an anodized metal oxide, such as an anodized aluminum oxide (AAO) thin film. The substrate insulating layer is then selectively etched to define a second array of nano-channels therein. This selective etching step preferably uses the etching template as an etching mask to transfer the first array of nano-channels to the underlying substrate insulating layer, which may be thinner than the etching template. An array of semiconductor nano-pillars is then formed in the second array of nano-channels. The semiconductor nano-pillars in the array may have an average diameter in a range between about 8 nm and about 50 nm. The semiconductor nano-pillars are also preferably homoepitaxial or heteroepitaxial with the semiconductor layer.

Abstract translation: 形成纳米级电子和光电子器件的方法包括在其中形成其中具有半导体层的衬底和在半导体层上的衬底绝缘层。 在衬底绝缘层上形成具有非光刻限定的纳米通道的第一阵列的蚀刻模板。 该蚀刻模板可以包括阳极氧化的金属氧化物，例如阳极氧化的氧化铝（AAO）薄膜。 然后选择性地蚀刻衬底绝缘层以在其中限定纳米通道的第二阵列。 该选择蚀刻步骤优选使用蚀刻模板作为蚀刻掩模，将第一纳米通道阵列转移到下面的衬底绝缘层，其可以比蚀刻模板更薄。 然后在第二纳米通道阵列中形成半导体纳米柱阵列。 阵列中的半导体纳米柱可以具有在约8nm和约50nm之间的范围内的平均直径。 半导体纳米柱也优选与半导体层同质外延或异质外延。

公开(公告)号：US20050153473A1

公开(公告)日：2005-07-14

申请号：US10510357

申请日：2003-04-04

Applicant: Jing Hua Teng ,  Soo Jin Chua ,  Jian Rong Dong

Inventor： Jing Hua Teng ,  Soo Jin Chua ,  Jian Rong Dong

IPC: H01L21/18 ,  H01L29/12 ,  H01L33/00 ,  H01S5/10 ,  H01S5/16 ,  H01S5/40 ,  H01L21/00

CPC classification number: B82Y10/00 ,  B82Y20/00 ,  H01L21/182 ,  H01L29/122 ,  H01L29/125 ,  H01L29/127 ,  H01L33/0095 ,  H01S5/1003 ,  H01S5/1092 ,  H01S5/162 ,  H01S5/3412 ,  H01S5/3414 ,  H01S5/4087

Abstract: A method for forming a modified semiconductor having a number of band gaps involves providing a semiconductor having a surface and a quantum region which emits photons in response to electrical or optical stimulation, the quantum region having an original band gap and being disposed under the surface and applying a number of layers of a number of materials to a number of selected regions of the surface, the materials being adapted to cause, upon thermal annealing, a number of different degrees of intermixing in a number of portions of the quantum region disposed immediately below each of the selected regions of the surface. The layers of materials can be applied in a dot or line pattern, or both, to increase the plurality of band gap tuning. The method includes thermally annealing the layers to the surface. The methods result in a modified semiconductor which exhibits a number of different band gaps in a number of portions of the quantum region depending upon the positioning of the layers of materials on the surface immediately above the respective portions of the quantum region.

Abstract translation: 用于形成具有多个带隙的修改的半导体的方法涉及提供具有表面的半导体和响应于电或光刺激而发射光子的量子区域，该量子区域具有原始带隙并设置在该表面下方， 将多个材料层施加到表面的多个选定区域，该材料适于在热退火时引起在紧邻下面布置的量子区域的多个部分中的多个不同程度的混合 每个表面的选定区域。 可以以点或线图案或两者来施加材料层以增加多个带隙调谐。 该方法包括将层热层退火到表面。 该方法产生一种修饰的半导体，其取决于材料层在量子区的相应部分上方的表面上的位置，在量子区的多个部分中表现出许多不同的带隙。

公开(公告)号：US06773949B2

公开(公告)日：2004-08-10

申请号：US10330692

申请日：2002-12-27

Applicant: Nick Holonyak, Jr. ,  Russell Dupuis

Inventor： Nick Holonyak, Jr. ,  Russell Dupuis

IPC: H01L2120

CPC classification number: H01L29/125 ,  B82Y10/00 ,  B82Y20/00 ,  H01L29/127 ,  H01L33/06 ,  H01S5/341 ,  H01S5/3412 ,  H01S5/3416 ,  H01S5/3425

Abstract: A method of forming a semiconductor device includes the following steps: providing a plurality of semiconductor layers; providing means for coupling signals to and/or from layers of the device; providing a layer of quantum dots disposed between adjacent layers of the device; and providing an auxiliary layer disposed in one of the adjacent layers, and spaced from the layer of quantum dots, the auxiliary layer being operative to communicate carriers with the layer of quantum dots.

公开(公告)号：US06683013B2

公开(公告)日：2004-01-27

申请号：US10099985

申请日：2002-03-19

Applicant: Eun Kyu Kim ,  Yong Ju Park ,  Hyo Jin Kim ,  Tae Whan Kim

Inventor： Eun Kyu Kim ,  Yong Ju Park ,  Hyo Jin Kim ,  Tae Whan Kim

IPC: H01L2100

CPC classification number: B82Y10/00 ,  H01L21/02392 ,  H01L21/02395 ,  H01L21/02433 ,  H01L21/02463 ,  H01L21/02546 ,  H01L21/0259 ,  H01L21/0262 ,  H01L29/125 ,  H01L29/127

Abstract: Disclosed is a method of forming a quantum dots array. In the method of the present invention, a structure of wire-like quantum dots with good quality is formed in materials having an inconsistency in the lattice constant on a tilted substrate by using the binding property of atomic bonding due to chemical bonding steps of the tilted substrate, and the spacing of the wire-like quantum dots is varied by using the step width of the tilted substrate which is transformed due to a partial pressure of a source gas and the thickness of a buffer layer. The invention allows materials having an inconsistency in the lattice constant to be freely formed in the form of quantum wires with a growing technique only and accordingly to be used as base materials in use for manufacture of novel concept of optoelectronic devices which have not been obtained so far.

Abstract translation: 公开了一种形成量子点阵列的方法。 在本发明的方法中，通过使用由于倾斜的化学键合步骤引起的原子键合的结合特性，在倾斜的基板上的晶格常数不一致的材料中形成质量好的线状量子点的结构 基板，并且通过使用由于源气体的分压和缓冲层的厚度而变换的倾斜基板的台阶宽度来改变线状量子点的间隔。 本发明允许具有晶格常数不一致的材料以量子线的形式自由地形成为仅具有成长技术的材料，并因此被用作用于制造尚未获得的光电子器件的新概念的基础材料 远。

公开(公告)号：US20030170927A1

公开(公告)日：2003-09-11

申请号：US10330692

申请日：2002-12-27

Applicant: The board Of Trustees Of The University Of Illinois

Inventor： Nick Holonyak JR. ,  Russell Dupuis

IPC: H01L021/00

CPC classification number: H01L29/125 ,  B82Y10/00 ,  B82Y20/00 ,  H01L29/127 ,  H01L33/06 ,  H01S5/341 ,  H01S5/3412 ,  H01S5/3416 ,  H01S5/3425

Abstract: A method of forming a semiconductor device includes the following steps: providing a plurality of semiconductor layers; providing means for coupling signals to and/or from layers of the device; providing a layer of quantum dots disposed between adjacent layers of the device; and providing an auxiliary layer disposed in one of the adjacent layers, and spaced from the layer of quantum dots, the auxiliary layer being operative to communicate carriers with the layer of quantum dots.

Abstract translation: 一种形成半导体器件的方法包括以下步骤：提供多个半导体层; 提供用于将信号耦合到和/或来自所述装置的层的装置; 提供设置在所述装置的相邻层之间的量子点层; 以及设置在相邻层之一中并与所述量子点的间隔开的辅助层，所述辅助层可操作以与所述量子点层传送载流子。

公开(公告)号：US20030059998A1

公开(公告)日：2003-03-27

申请号：US10209279

申请日：2002-07-31

Applicant: Trustees Of the University of Illinois

Inventor： Nick Holonyak JR. ,  Russell Dupuis

IPC: H01L021/8238

CPC classification number: B82Y20/00 ,  B82Y10/00 ,  H01L29/125 ,  H01L29/127 ,  H01L33/06 ,  H01S5/341 ,  H01S5/3412 ,  H01S5/3416 ,  H01S5/3425

Abstract: A method of forming a semiconductor device includes the following steps: providing a plurality of semiconductor layers; providing means for coupling signals to and/or from layers of the device; providing a quantum well disposed between adjacent layers of the device; and providing a layer of quantum dots disposed in one of the adjacent layers, and spaced from the quantum well, whereby carriers can tunnel in either direction between the quantum well and the quantum dots.

Abstract translation: 一种形成半导体器件的方法包括以下步骤：提供多个半导体层; 提供用于将信号耦合到和/或来自所述装置的层的装置; 提供设置在所述装置的相邻层之间的量子阱; 并且提供设置在相邻层之一中并与量子阱间隔开的量子点层，由此载流子可以在量子阱和量子点之间的任一方向上隧道。

公开(公告)号：US06242275B1

公开(公告)日：2001-06-05

申请号：US09137617

申请日：1998-08-21

Applicant: Sung Bock Kim ,  Jeong Rae Ro ,  El Hang Lee

Inventor： Sung Bock Kim ,  Jeong Rae Ro ,  El Hang Lee

IPC: H01L2120

CPC classification number: B82Y10/00 ,  H01L21/02395 ,  H01L21/02463 ,  H01L21/02494 ,  H01L21/02507 ,  H01L21/02546 ,  H01L21/0259 ,  H01L21/02609 ,  H01L29/125 ,  Y10S438/962

Abstract: A method for manufacturing quantum wires is provided in which a stacked structure having AlAs layers and GaAs layers alternatively is formed, V-grooves are formed beside the GaAs layers and the quantum wires are formed using the V-grooves. The method for manufacturing quantum wires, which method includes the following steps: growing a GaAs buffer layer on the facet (011) of a GaAs single crystal substrate; growing an AlAs layer for using as oxide mask and a GaAs layer for a V-groove alternatively on the GaAs buffer layer so that each GaAs layer is stacked between an AlAs layer and an adjacent AlAs layer; growing the cover layer of GaAs on the AlAs layer which is grown as the top layer of the structure; cutting the entire structure including the GaAs cover layer to the perpendicular direction of (011), whose structure is grown in the orientation of (011) entirely, so as to expose the facet (100); performing a heat treatment for the entire structure cut to expose the facet (100) and forming oxide film on the exposed portion of each AlAs layer; etching each exposed GaAs layer chemically using the oxide as mask and forming V-groove so that the facet (111) of GaAs layer is exposed; and growing the quantum wire in the V-groove.

Abstract translation: 提供一种制造量子线的方法，其中形成具有AlAs层和GaAs层的堆叠结构，在GaAs层旁边形成V沟槽，并且使用V形槽形成量子线。 制造量子线的方法，该方法包括以下步骤：在GaAs单晶衬底的面（011）上生长GaAs缓冲层; 在GaAs缓冲层上生长用作氧化物掩模和用于V沟槽的GaAs层的AlAs层，使得每个GaAs层堆叠在AlAs层和相邻的AlAs层之间; 在作为结构的顶层生长的AlAs层上生长GaAs覆盖层; 将包括GaAs覆盖层的整个结构切割成（011）的垂直方向，其结构全部沿着（011）的取向生长，从而露出小面（100）。 对整个结构进行热处理以暴露小面（100）并在每个AlAs层的暴露部分上形成氧化物膜; 使用氧化物作为掩模化学地蚀刻每个暴露的GaAs层并形成V形槽，使得GaAs层的面（111）暴露; 并在V槽中生长量子线。

公开(公告)号：US5917194A

公开(公告)日：1999-06-29

申请号：US684766

申请日：1996-07-17

Applicant: Mitra Dutta ,  Michael A. Stroscio ,  Gerald J. Iafrate ,  Ki Wook Kim ,  Yuri M. Sirenko

Inventor： Mitra Dutta ,  Michael A. Stroscio ,  Gerald J. Iafrate ,  Ki Wook Kim ,  Yuri M. Sirenko

IPC: H01L29/06 ,  H01L29/12 ,  H01L29/775 ,  H01L31/0352

CPC classification number: B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/125

Abstract: A mesoscopic structure is fabricated such that the desired dominant modes of the acoustic phonons in the structure have wavelengths such that the length of a half-integral number of wavelengths equals the length of the structure through which the desired electron wave is propagating. A manner of achieving this object is to provide for a material in a quantum wire and a material at the end of the quantum wire such that the two materials have such different properties (as disclosed hereinafter) to abruptly dampen the phonon modes at the interface between the two materials. With such an interface, a clamped boundary condition will occur and the modes of amplitude can be assumed to vanish at the interface. Such a case applies at some metal-semiconductor interfaces. In particular, for a mesoscopic device having wire-like regions which terminate on a variety of metal regions (regions used as contacts, gates, barriers, etc.), it is satisfactory to apply clamped boundary conditions. At these boundaries, the acoustic modes will have nodes instead of the anti-nodes that are established in the case of an open boundary.

Abstract translation: 制造介观结构，使得结构中声学声子的期望主要模式具有波长，使得半整数倍的波长的长度等于期望的电子波正在传播的结构的长度。 实现该目的的一种方式是提供量子线材料和量子线末端的材料，使得两种材料具有如下所述的不同性质（如下所述），以突然地抑制在第 两种材料。 通过这样的界面，会发生夹紧的边界条件，并且可以假定振幅的模式在界面处消失。 这种情况适用于某些金属 - 半导体界面。 特别地，对于具有终止于各种金属区域（用作触点，栅极，屏障等的区域）的线状区域的介观器件，施加夹持的边界条件是令人满意的。 在这些边界处，声学模式将具有节点而不是在开放边界的情况下建立的反节点。

公开(公告)号：US5828076A

公开(公告)日：1998-10-27

申请号：US727440

申请日：1996-10-17

Applicant: Harald Gossner ,  Ignaz Eisele ,  Lothar Risch ,  Erwin Hammerl

Inventor： Harald Gossner ,  Ignaz Eisele ,  Lothar Risch ,  Erwin Hammerl

IPC: H01L29/78 ,  B82B1/00 ,  H01L21/20 ,  H01L21/335 ,  H01L29/06 ,  H01L29/10 ,  H01L29/12 ,  H01L29/423

CPC classification number: H01L29/127 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02639 ,  H01L29/1054 ,  H01L29/125 ,  H01L29/66439 ,  H01L29/78

Abstract: In its gate region (10), a silicon MOS technology component has a surface structure (6) having edges and/or vertices at which inversion regions, suitable as quantum wires or quantum dots, are preferentially formed when a gate voltage is applied. The surface structure is preferably formed as a silicon pyramid (6) by local molecular beam epitaxy.

Abstract translation: PCT No.PCT / DE95 / 00448 Sec。 371日期1996年10月17日第 102（e）日期1996年10月17日PCT提交1995年4月4日PCT公布。 WO95 / 28741 PCT出版物 日期1995年10月26日在其栅极区域（10）中，硅MOS技术部件具有具有边缘和/或顶点的表面结构（6），当栅极（10）处优选形成适合作为量子线或量子点的反转区域 施加电压。 表面结构优选通过局部分子束外延形成为硅金字塔（6）。

公开(公告)号：US5804475A

公开(公告)日：1998-09-08

申请号：US665931

申请日：1996-06-19

Applicant: Jerry R. Meyer ,  Craig A. Hoffman ,  Filbert J. Bartoli, Jr.

Inventor： Jerry R. Meyer ,  Craig A. Hoffman ,  Filbert J. Bartoli, Jr.

IPC: H01L29/12 ,  H01L29/772 ,  H01L29/812 ,  H01L21/20 ,  H01L21/28

CPC classification number: B82Y10/00 ,  H01L29/125 ,  H01L29/772 ,  H01L29/8124 ,  Y10S438/962 ,  Y10S977/755 ,  Y10S977/759 ,  Y10S977/762 ,  Y10S977/891 ,  Y10S977/936

Abstract: This invention describes a nanometer scale interband lateral resonant tunneling transistor, and the method for producing the same, with lateral geometry, good fanout properties and suitable for incorporation into large-scale integrated circuits. The transistor is of a single gate design and operation is based on resonant tunneling processes in narrow-gap nanostructures which are highly responsive to quantum phenomena. Such quantum-effect devices can have very high density, operate at much higher temperatures and are capable of driving other devices.

Abstract translation: 本发明描述了一种纳米尺度的带间横向谐振隧道晶体管及其制造方法，具有侧向几何形状，良好的扇出特性，并且适合于并入大规模集成电路。 晶体管具有单栅极设计，并且操作基于对量子现象高度响应的窄间隙纳米结构中的谐振隧穿工艺。 这种量子效应器件可以具有非常高的密度，在高得多的温度下操作并且能够驱动其它器件。