公开(公告)号：US20050110016A1

公开(公告)日：2005-05-26

申请号：US11013516

申请日：2004-12-17

申请人： Shunpei Yamazaki

发明人： Shunpei Yamazaki

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786 ,  H01L31/112

CPC分类号： H01L27/3262 ,  H01L21/28114 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1222 ,  H01L27/3244 ,  H01L27/3248 ,  H01L29/42384 ,  H01L29/66492 ,  H01L29/66598 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/78675 ,  H01L29/78696 ,  H01L51/5256 ,  H01L2029/7863 ,  H01L2227/32

摘要： There is provided a thin film transistor having improved reliability. A gate electrode includes a first gate electrode having a taper portion and a second gate electrode with a width narrower than the first gate electrode. A semiconductor layer is doped with phosphorus of a low concentration through the first gate electrode. In the semiconductor layer, two kinds of n−-type impurity regions are formed between a channel formation region and n+-type impurity regions. Some of the n−-type impurity regions overlap with a gate electrode, and the other n−-type impurity regions do not overlap with the gate electrode. Since the two kinds of n−-type impurity regions are formed, an off current can be reduced, and deterioration of characteristics can be suppressed.

公开(公告)号：US06891195B2

公开(公告)日：2005-05-10

申请号：US10207822

申请日：2002-07-31

申请人： Shunpei Yamazaki ,  Jun Koyama

发明人： Shunpei Yamazaki ,  Jun Koyama

IPC分类号： H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L31/036 ,  H01L29/04 ,  H01L31/0376 ,  H01L31/112 ,  H01L31/20

CPC分类号： H01L29/78696 ,  H01L27/124 ,  H01L27/127 ,  H01L27/3262 ,  H01L29/4908 ,  H01L29/78621 ,  H01L29/78624 ,  H01L29/78627 ,  H01L33/0041 ,  H01L2029/7863

摘要： The purpose of the present invention is to provide a reliable semiconductor device comprising TFTs having a large area integrated circuit with low wiring resistance. One of the features of the present invention is that an LDD region including a region which overlaps with a gate electrode and a region which does not overlap with the gate electrode is provided in one TFT. Another feature of the present invention is that gate electrode comprises a first conductive layer and a second conductive layer and portion of the gate wiring has a clad structure comprising the first conductive layer and the second conductive layer with a low resistance layer interposed therebetween.

摘要翻译： 本发明的目的是提供一种包括具有低布线电阻的大面积集成电路的TFT的可靠的半导体器件。 本发明的特征之一是在一个TFT中设置包括与栅电极重叠的区域和不与栅电极重叠的区域的LDD区域。 本发明的另一特征在于，栅电极包括第一导电层和第二导电层，并且栅极布线的一部分具有包含第一导电层和第二导电层的包层结构，其间具有低电阻层。

公开(公告)号：US06882012B2

公开(公告)日：2005-04-19

申请号：US09794244

申请日：2001-02-28

申请人： Shunpei Yamazaki ,  Jun Koyama ,  Yasuyuki Arai

发明人： Shunpei Yamazaki ,  Jun Koyama ,  Yasuyuki Arai

IPC分类号： G02F1/13 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L27/32 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L23/62

CPC分类号： H01L27/1237 ,  G02F1/13452 ,  H01L27/1214 ,  H01L27/3244 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/78696 ,  H01L2029/7863 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48464 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/00

摘要： To form a driver circuit to be mounted to a liquid crystal display device or the like on a glass substrate, a quartz substrate, etc., and to provide a display device mounting driver circuits formed from different TFTs suited for their respective operational characteristics. A stick driver circuit on the scanning line side and a stick driver circuit on the data line side are different in structure, and have different TFTs in which the thickness of a gate insulating film, the channel length and other parameters are varied depending on required circuit characteristics. In the stick driver on the scanning line side, which is composed of a shift register circuit, a level shifter circuit, and a buffer circuit, the buffer circuit has a TFT with a thick gate insulating film because it is required to have a withstand voltage of 30 V. The stick driver circuit on the data line side, which is composed of a shift register circuit, a latch circuit, a level shifter circuit, and a D/A converter circuit, is driven at a high frequency, and hence its shift register circuit and latch circuit have thin gate insulating films and the channel length thereof is shorter than that of the TFT of the buffer circuit.

摘要翻译： 为了形成在玻璃基板，石英基板等上安装到液晶显示装置等的驱动电路，并且提供一种显示装置，其安装由适合其各自操作特性的不同TFT形成的驱动电路。 扫描线侧的棒状驱动电路和数据线侧的棒状驱动电路的结构不同，具有不同的TFT，栅极绝缘膜的厚度，沟道长度等参数根据所需电路而变化 特点 在由移位寄存器电路，电平移位器电路和缓冲电路组成的扫描线侧的棒驱动器中，缓冲电路具有厚栅极绝缘膜的TFT，因为需要具有耐电压 由移位寄存器电路，锁存电路，电平移位电路和D / A转换器电路组成的数据线侧的棒驱动电路以高频驱动，因此其 移位寄存器电路和锁存电路具有薄栅极绝缘膜，其沟道长度比缓冲电路的TFT的沟道长度短。

公开(公告)号：US06872658B2

公开(公告)日：2005-03-29

申请号：US10302693

申请日：2002-11-22

申请人： Etsuko Arakawa ,  Kiyoshi Kato ,  Yoshiyuki Kurokawa

发明人： Etsuko Arakawa ,  Kiyoshi Kato ,  Yoshiyuki Kurokawa

IPC分类号： H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786 ,  H01L21/44

CPC分类号： H01L29/78621 ,  H01L27/124 ,  H01L29/42384 ,  H01L2029/7863

摘要： A gate metal is formed in a film, the foregoing gate metal is partially etched per each TFT having a different property, and a gate electrode is fabricated. Specifically, a resist mask is fabricated by exposing a resist to light per each TFT having a different property which is required. A gate metal is etched per each TFT having a different property which is required using the foregoing resist mask. At this time, a gate metal covering a semiconductor active layer of a TFT except for the TFT during the time when the patterning of a gate electrode is performed is left as it is covered. The step of fabricating a gate electrode of each TFT may be performed under the conditions optimized in conformity with the required property.

摘要翻译： 在薄膜中形成栅极金属，每个具有不同性质的TFT部分地蚀刻上述栅极金属，并且制造栅电极。 具体地，通过使每个TFT具有不同性质的抗蚀剂曝光光来制造抗蚀剂掩模。 每个TFT蚀刻栅极金属，其具有使用上述抗蚀剂掩模所需的不同性质。 此时，在覆盖栅电极的图案形成时的TFT以外的覆盖TFT的半导体有源层的栅极金属被覆盖。 可以在根据所需性能优化的条件下进行制造每个TFT的栅电极的步骤。

公开(公告)号：US06872607B2

公开(公告)日：2005-03-29

申请号：US09812529

申请日：2001-03-20

申请人： Koichiro Tanaka

发明人： Koichiro Tanaka

IPC分类号： H01L21/20 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L21/00

CPC分类号： H01L21/02675 ,  H01L21/2026 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1285 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78636 ,  H01L29/78645 ,  H01L2029/7863

摘要： By using lasers having different wavelengths in laser annealing of an amorphous semiconductor film, the amorphous semiconductor film can be crystallized and the crystallinity of the crystallized film is improved. A laser 126 to 370 nm in wavelength is used first to subject an amorphous semiconductor film to laser annealing, thereby obtaining a crystalline semiconductor film. In desirable laser annealing, a subject surface is irradiated with a laser beam processed by an optical system into a linear laser beam that is linear in section on the subject surface. Next, a laser 370 to 650 nm in wavelength is used to irradiate the above crystalline semiconductor film by again processing the laser beam into a linear beam through an optical system. A crystalline semiconductor film thus obtained has an excellent crystallinity. If this crystalline semiconductor film is used to form an active layer of a TFT, an electric characteristic of the TFT can be improved.

摘要翻译： 通过在非晶半导体膜的激光退火中使用具有不同波长的激光，可以使非晶半导体膜结晶化，结晶化膜的结晶性提高。 首先使用波长为126〜370nm的激光，使非晶半导体膜进行激光退火，得到结晶半导体膜。 在期望的激光退火中，将由光学系统处理的激光束照射到被摄体表面上的直线激光束，该直线激光束在被摄体表面上呈截面线性。 接下来，通过将激光束再次通过光学系统处理成线性光束，使用波长为370nm至650nm的激光来照射上述晶体半导体膜。 由此获得的结晶半导体膜具有优异的结晶度。 如果使用这种晶体半导体膜来形成TFT的有源层，则可以提高TFT的电特性。

公开(公告)号：US20050040476A1

公开(公告)日：2005-02-24

申请号：US10935177

申请日：2004-09-08

申请人： Yasuhiko Takemura ,  Satoshi Teramoto

发明人： Yasuhiko Takemura ,  Satoshi Teramoto

IPC分类号： H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/13 ,  H01L29/786 ,  H01L29/04

CPC分类号： H01L27/1248 ,  H01L27/1255 ,  H01L29/66757 ,  H01L29/78621 ,  H01L2029/7863

摘要： A thin film transistor of the present invention has an active layer including at least source, drain and channel regions formed on an insulating surface. A high resistivity region is formed between the channel region and each of the source and drain regions. A film capable of trapping positive charges therein is provided on at least the high resistivity region so that N-type conductivity is induced in the high resistivity region. Accordingly, the reliability of N-channel type TFT against hot electrons can be improved.

摘要翻译： 本发明的薄膜晶体管具有至少包括形成在绝缘表面上的源极，漏极和沟道区的有源层。 在沟道区域和源极和漏极区域中的每一个之间形成高电阻率区域。 至少在高电阻率区域上设置能够俘获正电荷的膜，使得在高电阻率区域中产生N型导电性。 因此，可以提高N沟道型TFT对热电子的可靠性。

公开(公告)号：US06838698B1

公开(公告)日：2005-01-04

申请号：US08788560

申请日：1997-01-24

申请人： Shunpei Yamazaki ,  Yasuhiko Takemura

发明人： Shunpei Yamazaki ,  Yasuhiko Takemura

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/77 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/08 ,  H01L29/167 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76 ,  H01L27/01 ,  H01L29/04

CPC分类号： H01L29/78618 ,  H01L21/26506 ,  H01L21/823814 ,  H01L27/1214 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/6659 ,  H01L29/66757 ,  H01L29/7833 ,  H01L29/78675 ,  H01L2029/7863

摘要： A semiconductor device and a method for forming the same are disclosed. The semiconductor device comprising an insulated gate field effect transistor provided with a region having added thereto an element at least one selected from the group consisting of carbon, nitrogen, and oxygen, said region having established at either or both of the vicinity of the boundary between the drain and the semiconductor layer under the gate electrode and the vicinity of the boundary between the source and the semiconductor layer under the gate electrode for example by ion implantation using a mask. It is free from the problems of reverse leakage between the source and the drain, and of throw leakage which occurs even at a voltage below the threshold ascribed to the low voltage resistance between the source and the drain.

摘要翻译： 公开了半导体器件及其形成方法。 该半导体器件包括绝缘栅场效应晶体管，该晶体管具有向其中添加了选自碳，氮和氧的组中的至少一种的元素的区域，所述区域建立在碳，氮和氧之间的边界附近的一个或两个附近 漏极和半导体层以及栅电极下的源极和半导体层之间的边界附近，例如通过使用掩模的离子注入。 在源极和漏极之间的低电压电阻下，即使在低于阈值的电压下也可以产生漏极和漏极之间的泄漏问题。

公开(公告)号：US20040214439A1

公开(公告)日：2004-10-28

申请号：US10852258

申请日：2004-05-25

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei Yamazaki

IPC分类号： G02F001/1335

CPC分类号： H01L21/02675 ,  G02F1/13454 ,  H01L21/02672 ,  H01L21/2026 ,  H01L21/3003 ,  H01L27/1255 ,  H01L27/3244 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78645 ,  H01L2029/7863

摘要： A semiconductor device having high operating performance and reliability, and a manufacturing method thereof are provided. An LDD region 207 provided in an n-channel TFT 302 forming a driving circuit enhances the tolerance for hot carrier injection. LDD regions 217-220 provided in an n-channel TFT (pixel TFT) 304 forming a pixel portion greatly contribute to the decrease in the OFF current value. Here, the LDD region of the n-channel TFT of the driving circuit is formed such that the concentration of the n-type impurity element becomes higher as the distance from an adjoining drain region decreases.

摘要翻译： 提供了具有高操作性能和可靠性的半导体器件及其制造方法。 设置在形成驱动电路的n沟道TFT 302中的LDD区域207增强了热载流子注入的容限。 设置在形成像素部的n沟道TFT（像素TFT）304中的LDD区域217-220极大地有助于关断电流值的降低。 这里，驱动电路的n沟道TFT的LDD区域形成为随着与邻接的漏极区的距离减小，n型杂质元素的浓度变高。

公开(公告)号：US20040209409A1

公开(公告)日：2004-10-21

申请号：US10731000

申请日：2003-12-10

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shigeharu Monoe ,  Takashi Yokoshima ,  Shinya Sasagawa

IPC分类号： H01L021/00

CPC分类号： H01L29/66757 ,  H01L21/32136 ,  H01L21/32139 ,  H01L29/42384 ,  H01L29/78621 ,  H01L2029/7863

摘要： With respect to the selective ratio in the etching process, it is an object to give design freedom in size of an LDD overlapped with a gate electrode, which is formed in a self-aligning manner, by performing an etching process under an etching condition that has a high selective ratio between a mask pattern and metal such as titanium in forming a first conductive layer pattern. A laminated structure comprising a lower first conductive layer and an upper second conductive layer is formed over a semiconductor layer with a gate insulating film interposed therebetween, a mask pattern is formed on the laminated structure, a condition that an etching rate of the mask pattern is fast is used and the second conductive layer and the first conductive layer are etched to form a tapered first conductive layer pattern, and the second conductive layer in the first conductive layer pattern is selectively etched in accordance with the left mask pattern to form a second conductive layer pattern in which a width of the first conductive layer is longer than that of the second conductive layer.

摘要翻译： 关于蚀刻工艺中的选择比，目的是通过在蚀刻条件下进行蚀刻工艺，以自对准方式形成与栅电极重叠的LDD的尺寸设计自由度， 在形成第一导电层图案时，在掩模图案和诸如钛的金属之间具有高的选择比。 在半导体层上形成包括下部第一导电层和上部第二导电层的层叠结构，其间具有栅极绝缘膜，在层叠结构上形成掩模图案，掩模图案的蚀刻速率为 并且第二导电层和第一导电层被蚀刻以形成渐缩的第一导电层图案，并且根据左掩模图案选择性地蚀刻第一导电层图案中的第二导电层以形成第二导电层 所述第一导电层的宽度比所述第二导电层的宽度长。

公开(公告)号：US20040206974A1

公开(公告)日：2004-10-21

申请号：US10838267

申请日：2004-05-05

申请人： Semiconductor Energy Laboratory, Co., Ltd. .

发明人： Shunpei Yamazaki ,  Jun Koyama ,  Hideomi Suzawa ,  Koji Ono ,  Tatsuya Arao

IPC分类号： H01L033/00 ,  H01L029/04 ,  H01L035/24 ,  H01L029/76

CPC分类号： H01L27/1222 ,  G02F1/13454 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/127 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78621 ,  H01L2029/7863

摘要： A high reliability semiconductor display device is provided. A semiconductor layer in the semiconductor display device has a channel forming region, an LDD region, a source region, and a drain region, and the LDD region overlaps a first gate electrode, sandwiching a gate insulating film.

摘要翻译： 提供了一种高可靠性的半导体显示装置。 半导体显示装置中的半导体层具有沟道形成区域，LDD区域，源极区域和漏极区域，并且LDD区域与第一栅极电极重叠，夹着栅极绝缘膜。