公开(公告)号：US20170269989A1

公开(公告)日：2017-09-21

申请号：US15244363

申请日：2016-08-23

Applicant: SK hynix Inc.

Inventor： Jong Sam KIM

IPC: G06F11/07 ,  G11C11/406 ,  G11C29/00 ,  G11C17/16

CPC classification number: G06F11/0793 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/079 ,  G06F11/1048 ,  G11C11/406 ,  G11C17/16 ,  G11C29/50 ,  G11C29/76 ,  G11C2029/0411 ,  G11C2029/4402

Abstract: A semiconductor device may include normal memory cells, redundancy memory cells, a fuse array, and a controller. The normal memory cells may be coupled to a plurality of word lines and bit lines. The redundancy memory cells may be coupled to a plurality of word lines and bit lines, and may replace one or more normal memory cells that are defective. The fuse array may include a redundancy address storage region configured to store addresses of the redundancy memory cells, an error correction information storage region configured to store error correction information for correcting errors of addresses of the redundancy memory cells, stored in the redundancy address storage region, and a weak address storage region configured to store an address of a weak cell among the normal memory cells. The controller may perform a repair operation based on a redundancy address and perform a refresh operation on a weak cell corresponding to the address of the weak cell.

公开(公告)号：US20170263610A9

公开(公告)日：2017-09-14

申请号：US14731764

申请日：2015-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HAN-SIK YOO ,  HYUK-JOON KWON ,  JUNG-HA OH ,  JUN-HO KIM

IPC: H01L27/108 ,  H01L23/528 ,  H01L49/02

CPC classification number: H01L27/10823 ,  G06F11/1048 ,  G11C11/5635 ,  G11C11/5671 ,  G11C16/0466 ,  G11C29/42 ,  G11C29/52 ,  G11C2029/0411 ,  H01L23/528 ,  H01L27/10814 ,  H01L27/11582 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate, a memory structure and a capacitor structure including at least one array of capacitors. The memory structure is disposed in a first region of the device. The capacitor structure is disposed in a second region of the device. The capacitor structure may include a first capacitor array, a second capacitor array, a third capacitor array and a first landing pad. The first landing pad is disposed between the substrate and lower electrodes of capacitors of the first and second capacitor arrays, and contacts the lower electrodes so as to electrically connect the first capacitor array and the second capacitor array. Upper electrodes of capacitors of the second and third capacitor arrays are integral such that the second capacitor array and the third capacitor array are electrically connected to each other.

公开(公告)号：US09761308B1

公开(公告)日：2017-09-12

申请号：US15068427

申请日：2016-03-11

Applicant: HGST Netherlands B.V.

Inventor： Aldo G. Cometti

IPC: G06F11/00 ,  G11C11/56 ,  G11C16/26 ,  G06F11/07

CPC classification number: G11C11/5642 ,  G06F11/0727 ,  G06F11/076 ,  G06F11/079 ,  G06F11/0793 ,  G06F11/1048 ,  G11C16/26 ,  G11C29/50004 ,  G11C29/52 ,  G11C2029/0411

Abstract: Reading requested data from flash memory using a first read level voltage. A number of first bit-value errors and a number of second bit-value errors is determined from the read requested data. An error ratio of the number of first bit-value errors and the number of second bit-value errors is compared to an error-ratio range. The first level voltage is adjusted based on the comparison of the error ratio to the error-ratio range.

公开(公告)号：US20170255531A1

公开(公告)日：2017-09-07

申请号：US15600408

申请日：2017-05-19

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Gary Gostin ,  Erin A. Handgen

IPC: G06F11/16 ,  G06F3/06 ,  G06F11/10 ,  G11C29/00

CPC classification number: G06F11/1666 ,  G06F3/0619 ,  G06F3/0658 ,  G06F3/0683 ,  G06F11/1064 ,  G06F11/1068 ,  G11C29/74 ,  G11C29/808 ,  G11C2029/0411

Abstract: Techniques are provided for overcoming failures in a memory. One portion of the memory may operate in a single chip spare mode. Upon detection of an error in a single chip in the portion of the memory, a region of the portion of the memory may be converted to operate in a double chip spare mode. The memory may be accessed in both single and double chip spare modes.

公开(公告)号：US09754685B2

公开(公告)日：2017-09-05

申请号：US14829634

申请日：2015-08-18

Applicant: LAPIS Semiconductor Co., Ltd.

Inventor： Toshiharu Okada

IPC: G06F3/06 ,  G11C29/52 ,  G06F11/10 ,  G11C7/20 ,  G11C29/04

CPC classification number: G11C29/52 ,  G06F11/1048 ,  G11C7/20 ,  G11C2029/0407 ,  G11C2029/0411

Abstract: A memory device is operative to reset write-in status or read-out status information data in accordance with a reset signal. In response to the reset signal, a memory control device refers to a power-on reset check region in a RAM and determines whether or not the received reset signal is a power-on reset signal that is the reset signal generated firstly after power on. If the reset signal is determined to be the power-on reset signal, a memory check process is executed on respective target pages in each block in the memory. A refresh process is also performed on a block in which the number of error bits detected in the memory check process is more than a threshold value. The memory check process is performed on a different page whenever power is supplied.

公开(公告)号：US09754683B2

公开(公告)日：2017-09-05

申请号：US13977011

申请日：2012-03-29

Applicant: Matthew Goldman ,  Krishna K. Parat ,  Pranav Kalavade ,  Nathan R. Franklin ,  Mark Helm

Inventor： Matthew Goldman ,  Krishna K. Parat ,  Pranav Kalavade ,  Nathan R. Franklin ,  Mark Helm

IPC: G11C29/00 ,  G11C29/50 ,  G11C16/26 ,  G11C16/34 ,  G06F11/10 ,  G11C11/56 ,  G11C29/04

CPC classification number: G11C29/50004 ,  G06F11/1048 ,  G06F11/1068 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/34 ,  G11C2029/0411 ,  G11C2029/5004

Abstract: An apparatus may include a processor circuit a processor circuit to retrieve data from a non-volatile memory, and a multistrobe read module operable on the processor circuit to set a read operation to read a memory cell over a multiplicity of sense operations, where each sense operation is performed under a different sense condition. The multistrobe read module may be further operable to schedule a new sense operation to succeed a prior sense operation of the multiplicity of sense operations without recharge of the wordline when a value of one or more read condition is within a preset range. Other embodiments are disclosed and claimed.

公开(公告)号：US20170250694A1

公开(公告)日：2017-08-31

申请号：US15193357

申请日：2016-06-27

Applicant: SK hynix Inc.

Inventor： Da In IM ,  Young Suk SEO

IPC: H03L7/081 ,  G11C29/00 ,  G11C7/22 ,  H03L7/18

CPC classification number: H03L7/0812 ,  G11C7/222 ,  G11C29/52 ,  G11C29/787 ,  G11C2029/0411 ,  H03L7/0816 ,  H03L7/16 ,  H03L7/18

Abstract: A synchronization circuit may include: a delay line configured to delay a reference clock signal; a division circuit configured to generate a divided feedback clock signal by dividing a feedback clock signal at a division ratio which is set according to a division ratio control signal; a phase detection circuit configured to generate a phase detection signal by detecting the phase of the divided feedback clock signal based on the reference clock signal; and a delay line control circuit configured to control a delay time of the delay line according to the phase detection signal and the divided feedback clock signal.

公开(公告)号：US20170249208A1

公开(公告)日：2017-08-31

申请号：US15219380

申请日：2016-07-26

Applicant: SK hynix Inc.

Inventor： Jae Bum KIM

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1048 ,  G11C16/26 ,  G11C29/021 ,  G11C29/028 ,  G11C29/42 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/152 ,  H03M13/2909 ,  H03M13/296

Abstract: A data storage device includes a nonvolatile memory device including a target memory region; and a controller suitable for performing a read operation by reading a data chunk from the target memory region based on a read bias and performing an error correction operation for the data chunk, iterating the read operation according to a result of the error correction operation, and adjusting the read bias based on at least one read bias used in one or more previous read operations and at least one correction failure index corresponding to the at least one read bias.

公开(公告)号：US20170235637A1

公开(公告)日：2017-08-17

申请号：US15583678

申请日：2017-05-01

Applicant: Micron Technology, Inc.

Inventor： Violante Moschiano ,  Walter Di Francesco ,  Luca De Santis ,  Giovanni Santin

IPC: G06F11/10

CPC classification number: G06F11/1076 ,  G06F11/1048 ,  G06F11/1068 ,  G11C29/02 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/1102 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/3715 ,  H03M13/45

Abstract: A memory device includes a memory array that includes a buffer data. The memory device also includes a memory controller. The memory controller includes an error correction code (ECC) component. The memory controller further receives a status command and an indication related to the quality of the data to analyze with the ECC component. Based on a status value, the memory controller utilizes one of a plurality of error correction techniques via the ECC component to correct an error (e.g., soft state, calibration, etc.).

公开(公告)号：US09734008B2

公开(公告)日：2017-08-15

申请号：US14724901

申请日：2015-05-29

Applicant: International Business Machines Corporation

Inventor： Michael B. Healy ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Kyu-hyoun Kim ,  Warren E. Maule

IPC: G06F11/10 ,  G06F11/08 ,  G06F3/06 ,  G11C29/52 ,  G11C7/10 ,  G11C29/04

CPC classification number: G06F11/1008 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  G06F11/08 ,  G06F11/1032 ,  G06F11/1048 ,  G06F11/106 ,  G06F11/1072 ,  G06F11/1076 ,  G11C7/1006 ,  G11C7/1051 ,  G11C29/52 ,  G11C2029/0411

Abstract: A memory management system and method of managing output data resulting from a memory device storing raw data and error correction coding (ECC) bits are described. The system includes a controller to receive a read command and control a memory device based on the read command, the memory device to store raw data and error correction coding (ECC) bits and output the raw data and the ECC bits corresponding with memory addresses specified in the read command, and an ECC decoder to output an error vector associated with the memory addresses based on the raw data and the ECC bits corresponding with the memory addresses output by the memory device, the error vector associated with the memory addresses indicating errors in the raw data corresponding with the memory addresses. The system also includes a multiplexer (MUX) to output the error vector based on a selection indicated in the read command.