-
公开(公告)号：US20150338456A1
公开(公告)日：2015-11-26
申请号：US14816591
申请日：2015-08-03
Applicant: SK hynix Inc.
Inventor： Young Suk SEO , Ho Uk SONG , Jun Hyun CHUN , Tae Jin KANG
CPC classification number: G01R31/2644 , G01R31/2607 , G11C7/222 , G11C29/023 , G11C29/028 , G11C29/12015 , G11C29/50012 , H03L1/00 , H03L7/06
Abstract: A semiconductor apparatus includes: an output timing controller configured to delay an applied external read command by a predetermined time and generate a normal output enable flag signal, during a normal mode, a test output timing controller configured to generate a DLL clock signal from an external clock signal, delay the applied external read command in synchronization with the DLL clock signal, and output the delayed applied external read command as a test output enable flag signal, during a test mode, and a multiplexer (MUX) configured to output any one of the normal output enable flag signal or the test output enable flag signal as an output enable flag signal.
Abstract translation: 一种半导体装置，包括：输出定时控制器，被配置为将施加的外部读取命令延迟预定时间，并且在正常模式期间产生正常输出使能标志信号，所述测试输出定时控制器被配置为从外部产生DLL时钟信号 时钟信号，与DLL时钟信号同步地延迟施加的外部读取命令，并且在测试模式期间输出延迟的外部应用外部读取命令作为测试输出使能标志信号，以及多路复用器（MUX），其被配置为输出任何一个 正常输出使能标志信号或测试输出使能标志信号作为输出使能标志信号。
-
公开(公告)号：US20210013894A1
公开(公告)日：2021-01-14
申请号：US17036861
申请日：2020-09-29
Applicant: SK hynix Inc.
Inventor： Da In IM , Young Suk SEO
Abstract: A phase detection circuit is configured to receive an input clock signal and a reference clock signal. The phase detection circuit is configured to generate a divided clock signal from the reference clock signal. The phase detection circuit is configured to generate a phase detection signal after comparing the phase of the input clock signal with the divided clock signal.
-
3.发明申请公开(公告)号：US20200244276A1
公开(公告)日：2020-07-30
申请号：US16850738
申请日：2020-04-16
Applicant: SK hynix Inc.
Inventor： Da In IM , Young Suk SEO
Abstract: A phase detection circuit is configured to receive an input clock signal and a reference clock signal. The phase detection circuit is configured to generate a divided clock signal from the reference clock signal. The phase detection circuit is configured to generate a phase detection signal after comparing the phase of the input clock signal with the divided clock signal.
-
公开(公告)号：US20150365078A1
公开(公告)日：2015-12-17
申请号：US14458355
申请日：2014-08-13
Applicant: SK hynix Inc.
Inventor： Young Suk SEO , Da In IM
CPC classification number: H03L7/085 , H03L7/0814
Abstract: A regulation circuit of a semiconductor apparatus includes a control block configured to generate control signals in response to a reference clock signal and a feedback clock signal; and a noise compensation block configured to compensate for a variation in a level of power in response to the control signals.
Abstract translation: 半导体装置的调节电路包括：控制块，被配置为响应于参考时钟信号和反馈时钟信号产生控制信号; 以及噪声补偿块，被配置为响应于所述控制信号来补偿功率电平的变化。
-
公开(公告)号：US20140152358A1
公开(公告)日：2014-06-05
申请号：US13846756
申请日：2013-03-18
Applicant: SK HYNIX INC.
Inventor： Young Suk SEO
IPC: H03K3/017
CPC classification number: H03K5/1565
Abstract: A semiconductor apparatus includes a duty cycle correction block and a delay locked loop. The duty cycle correction block generates a duty corrected clock by correcting a duty cycle of an internal clock, adjusts a phase of a rising edge of the duty corrected clock when a delay locked loop is reset, and adjusts a phase of a falling edge of the duty corrected clock when the delay locked loop is locked. The delay locked loop receives an external clock to output the internal clock, and delays the external clock by a variable delay amount to output the internal clock when the adjustment of the phase of the rising edge of the duty corrected clock by the duty cycle correction block is completed.
Abstract translation: 半导体装置包括占空比校正块和延迟锁定环。 占空比校正块通过校正内部时钟的占空比来产生占空比校正时钟，当延迟锁定环被复位时，调整占空比校正时钟的上升沿的相位，并且调整下降沿的相位 延迟锁定环被锁定时的占空比校正时钟。 延迟锁定环接收外部时钟以输出内部时钟，并且通过占空比校正块调整占空比校正时钟的上升沿的相位来调节外部时钟一个可变延迟量以输出内部时钟 完成了。
-
Patent Agency Ranking
公开(公告)号：US20210013875A1
公开(公告)日：2021-01-14
申请号：US17034647
申请日：2020-09-28
Applicant: SK hynix Inc.
Inventor： Young Suk SEO
Abstract: A semiconductor apparatus includes a first clock path which generates a first output clock signal by delaying a first phase clock signal, and a second clock path which generates a second output clock signal by delaying a second phase clock signal based on a delay compensation signal. The oscillating path generation circuit forms oscillating paths with the first clock path and the second clock path. The delay information generation circuit generates a delay compensation signal based on oscillating signals generated by forming the oscillating paths.
-
7.发明申请公开(公告)号：US20200153421A1
公开(公告)日：2020-05-14
申请号：US16444799
申请日：2019-06-18
Applicant: SK hynix Inc.
Inventor： Young Suk SEO
Abstract: A semiconductor apparatus includes a first clock path which generates a first output clock signal by delaying a first phase clock signal, and a second clock path which generates a second output clock signal by delaying a second phase clock signal based on a delay compensation signal. The oscillating path generation circuit forms oscillating paths with the first clock path and the second clock path. The delay information generation circuit generates a delay compensation signal based on oscillating signals generated by forming the oscillating paths.
-
公开(公告)号：US20170250694A1
公开(公告)日：2017-08-31
申请号：US15193357
申请日：2016-06-27
Applicant: SK hynix Inc.
Inventor： Da In IM , Young Suk SEO
CPC classification number: H03L7/0812 , G11C7/222 , G11C29/52 , G11C29/787 , G11C2029/0411 , H03L7/0816 , H03L7/16 , H03L7/18
Abstract: A synchronization circuit may include: a delay line configured to delay a reference clock signal; a division circuit configured to generate a divided feedback clock signal by dividing a feedback clock signal at a division ratio which is set according to a division ratio control signal; a phase detection circuit configured to generate a phase detection signal by detecting the phase of the divided feedback clock signal based on the reference clock signal; and a delay line control circuit configured to control a delay time of the delay line according to the phase detection signal and the divided feedback clock signal.
-
9.发明申请CLOCK GENERATION CIRCUIT AND METHOD AND SEMICONDUCTOR APPARATUS AND ELECTRONIC SYSTEM USING THE SAME 有权时钟发生电路及其使用方法和半导体装置及电子系统公开(公告)号：US20170005782A1
公开(公告)日：2017-01-05
申请号：US14845425
申请日：2015-09-04
Applicant: SK hynix Inc.
Inventor： Da In IM , Young Suk SEO
CPC classification number: H03L7/0812 , H03L7/08 , H03L7/0814 , H04L7/0045 , H04L7/048
Abstract: A clock generation circuit may include a reference clock generator configured to generate a pair of first reference clocks in an offset code generation mode, a triggering unit configured to generate a pair of second reference clocks from the pair of first reference clocks, a pulse detector configured to generate a duty detection signal based on a phase difference between the pair of second reference clocks, a correction code generator configured to generate a reference correction code based on the duty detection signal, and an offset code generator configured to generate an offset code based on the reference correction code and a preset reference code.
Abstract translation: 时钟生成电路可以包括：参考时钟发生器，被配置为以偏移码生成模式生成一对第一参考时钟;触发单元，被配置为从所述一对第一参考时钟生成一对第二参考时钟;脉冲检测器， 基于所述一对第二参考时钟之间的相位差产生占空比检测信号，所述校正码发生器被配置为基于所述占空比检测信号生成参考校正码;以及偏移码发生器，被配置为生成基于 参考校正码和预设参考码。
-
公开(公告)号：US20150015310A1
公开(公告)日：2015-01-15
申请号：US14040829
申请日：2013-09-30
Applicant: SK HYNIX INC.
Inventor： Young Suk SEO
CPC classification number: H03L7/085 , H03L7/06 , H03L7/0812 , H03L7/0816
Abstract: Provided is a clock delay detecting circuit and semiconductor apparatus using the same that is capable of generating a period signal whose period is a delay time of a clock, dividing the period signal, and counting the divided period signal. The clock delay detection circuit comprises a period signal generating unit configured to generate a counting control signal, a period signal dividing unit configured to generate a counting enable signal by dividing the counting control signal, and a counting unit configured to generate a delay information signal by counting the counting enable signal with a clock, wherein the counting control signal has a period with a predetermined time.
-
-
-
-
-
-
-
-
-
Search Results
26
records
(took 0.102 seconds)
