公开(公告)号：US20170263610A9

公开(公告)日：2017-09-14

申请号：US14731764

申请日：2015-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HAN-SIK YOO ,  HYUK-JOON KWON ,  JUNG-HA OH ,  JUN-HO KIM

IPC: H01L27/108 ,  H01L23/528 ,  H01L49/02

CPC classification number: H01L27/10823 ,  G06F11/1048 ,  G11C11/5635 ,  G11C11/5671 ,  G11C16/0466 ,  G11C29/42 ,  G11C29/52 ,  G11C2029/0411 ,  H01L23/528 ,  H01L27/10814 ,  H01L27/11582 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate, a memory structure and a capacitor structure including at least one array of capacitors. The memory structure is disposed in a first region of the device. The capacitor structure is disposed in a second region of the device. The capacitor structure may include a first capacitor array, a second capacitor array, a third capacitor array and a first landing pad. The first landing pad is disposed between the substrate and lower electrodes of capacitors of the first and second capacitor arrays, and contacts the lower electrodes so as to electrically connect the first capacitor array and the second capacitor array. Upper electrodes of capacitors of the second and third capacitor arrays are integral such that the second capacitor array and the third capacitor array are electrically connected to each other.