公开(公告)号：US10050024B2

公开(公告)日：2018-08-14

申请号：US15370865

申请日：2016-12-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Jui-Pin Hung ,  Feng-Cheng Hsu ,  Shuo-Mao Chen ,  Shin-Puu Jeng

IPC: H01L23/48 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00

Abstract: The present disclosure provides a semiconductor package, including a first layer, a second layer, and a conductive array. The first layer includes a packaged die having a carrier surface and a molding surface, and a first die structure in proximity to the carrier surface. An active region of the first die structure is electrically coupled to the packaged die through a solder. The second layer includes a second die structure, the second die structure being connected to the active region of the first die structure by a first redistributed layer (RDL). The conductive array is connected to an active region of the second die structure by a second RDL. The present disclosure also provides a method for manufacturing the aforesaid semiconductor package.

公开(公告)号：US20180226378A1

公开(公告)日：2018-08-09

申请号：US15942807

申请日：2018-04-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jui-Pin Hung ,  Feng-Cheng Hsu ,  Shin-Puu Jeng

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/00 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/56

CPC classification number: H01L25/0652 ,  H01L21/31053 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76885 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/02311 ,  H01L2224/0237 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/81815 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83

Abstract: A method includes forming a first plurality of redistribution lines, forming a first metal post over and electrically connected to the first plurality of redistribution lines, and bonding a first device die to the first plurality of redistribution lines. The first metal post and the first device die are encapsulated in a first encapsulating material. The first encapsulating material is then planarized. The method further includes forming a second metal post over and electrically connected to the first metal post, attaching a second device die to the first encapsulating material through an adhesive film, encapsulating the second metal post and the second device die in a second encapsulating material, planarizing the second encapsulating material, and forming a second plurality of redistributions over and electrically coupling to the second metal post and the second device die.

公开(公告)号：US20180197755A1

公开(公告)日：2018-07-12

申请号：US15911893

申请日：2018-03-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Feng-Cheng Hsu ,  Shuo-Mao Chen ,  Jui-Pin Hung ,  Shin-Puu Jeng

IPC: H01L21/56 ,  H01L23/00 ,  H01L21/78 ,  H01L23/31

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/00 ,  H01L24/02 ,  H01L24/19 ,  H01L24/83 ,  H01L24/97 ,  H01L25/00 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2224/81 ,  H01L2224/83

Abstract: An embodiment device package includes a first die, a second die, and a molding compound extending along sidewalls of the first die and the second die. The package further includes redistribution layers (RDLs) extending laterally past edges of the first die and the second die. The RDLs include an input/output (I/O) contact electrically connected to the first die and the second die, and the I/O contact is exposed at a sidewall of the device package substantially perpendicular to a surface of the molding compound opposite the RDLs.

公开(公告)号：US20170229433A1

公开(公告)日：2017-08-10

申请号：US15495017

申请日：2017-04-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Po-Hao Tsai ,  Feng-Cheng Hsu ,  Li-Hui Cheng ,  Jui-Pin Hung ,  Jing-Cheng Lin

IPC: H01L25/10

CPC classification number: H01L25/105 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/8221 ,  H01L23/31 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/315 ,  H01L24/19 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/117 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00

Abstract: A bottom package includes a molding compound, a buffer layer over and contacting the molding compound, and a through-via penetrating through the molding compound. A device die is molded in the molding compound. A guiding trench extends from a top surface of the buffer layer into the buffer layer, wherein the guiding trench is misaligned with the device die.

公开(公告)号：US20170229322A1

公开(公告)日：2017-08-10

申请号：US15225083

申请日：2016-08-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Feng-Cheng Hsu ,  Shuo-Mao Chen ,  Jui-Pin Hung ,  Shin-Puu Jeng

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L21/78

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/19 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2224/81 ,  H01L2224/83

Abstract: An embodiment device package includes a first die, a second die, and a molding compound extending along sidewalls of the first die and the second die. The package further includes redistribution layers (RDLs) extending laterally past edges of the first die and the second die. The RDLs include an input/output (I/O) contact electrically connected to the first die and the second die, and the I/O contact is exposed at a sidewall of the device package substantially perpendicular to a surface of the molding compound opposite the RDLs.