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    Systems and methods of forming a reduced capacitance device
    82.
    发明授权
    Systems and methods of forming a reduced capacitance device 有权
    形成减电容器件的系统和方法

    公开(公告)号：US09472453B2

    公开(公告)日：2016-10-18

    申请号：US14471086

    申请日：2014-08-28

    Applicant: QUALCOMM Incorporated

    Inventor： Jeffrey Junhao Xu ,  John Jianhong Zhu ,  Stanley Seungchul Song ,  Kern Rim ,  Choh Fei Yeap

    IPC: H01L21/44 ,  H01L21/768 ,  H01L21/311

    CPC classification number: H01L21/76879 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76885

    Abstract: A method includes forming an electronic device structure including a substrate, an oxide layer, and a first low-k layer. The method also includes forming openings by patterning the oxide layer, filling the openings with a conductive material to form conductive structures within the openings, and removing the oxide layer using the first low-k layer as an etch stop layer. The conductive structures contact the first low-k layer. Removing the oxide layer includes performing a chemical vapor etch process with respect to the oxide layer to form an etch byproduct and removing the etch byproduct. The method includes forming a second low-k layer using a deposition process that causes the second low-k layer to define one or more cavities. Each cavity is defined between a first conductive structure and an adjacent conductive structure, the first and second conductive structures have a spacing therebetween that is smaller than a threshold distance.

    Abstract translation: 一种方法包括形成包括衬底，氧化物层和第一低k层的电子器件结构。 该方法还包括通过图案化氧化物层来形成开口，用导电材料填充开口以在开口内形成导电结构，以及使用第一低k层作为蚀刻停止层去除氧化物层。 导电结构接触第一低k层。 去除氧化物层包括相对于氧化物层执行化学气相蚀刻工艺以形成蚀刻副产物并除去蚀刻副产物。 该方法包括使用使第二低k层限定一个或多个空腔的沉积工艺形成第二低k层。 每个空腔限定在第一导电结构和相邻的导电结构之间，第一和第二导电结构之间具有小于阈值距离的间隔。

    Air gap between tungsten metal lines for interconnects with reduced RC delay
    83.
    发明授权
    Air gap between tungsten metal lines for interconnects with reduced RC delay 有权
    用于互连的钨金属线之间的空气间隙，具有减小的RC延迟

    公开(公告)号：US09425096B2

    公开(公告)日：2016-08-23

    申请号：US14330950

    申请日：2014-07-14

    Applicant: QUALCOMM Incorporated

    Inventor： Shiqun Gu ,  Matthew Michael Nowak ,  Jeffrey Junhao Xu

    IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/14 ,  H01L23/498

    CPC classification number: H01L21/76895 ,  H01L21/7682 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5222 ,  H01L23/53257 ,  H01L23/53295 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

    Abstract: Systems and methods are directed to a semiconductor device, which includes an integrated circuit, wherein the integrated circuit includes at least a first layer comprising two or more Tungsten lines and at least one air gap between at least two Tungsten lines, the air gaps to reduce capacitance. An interposer is coupled to the integrated circuit, to reduce stress on the two or more Tungsten lines and the at least one air gap. A laminated package substrate may be attached to the interposer such that the interposer is configured to absorb mechanical stress induced by mismatch in coefficient of thermal expansion (CTE) between the laminated package substrate and the interposer and protect the air gap from the mechanical stress.

    Abstract translation: 系统和方法涉及包括集成电路的半导体器件，其中集成电路至少包括包含两条或更多条钨线的至少一条第一层和至少两条钨线之间的至少一个气隙，所述气隙减少 电容。 插入器耦合到集成电路，以减少两个或多个钨线和至少一个气隙的应力。 层叠封装基板可以附接到插入件，使得插入件被构造成吸收由层压封装基板和插入件之间的热膨胀系数（CTE）失配引起的机械应力，并保护气隙免受机械应力。

    TIE-OFF STRUCTURES FOR MIDDLE-OF-LINE (MOL) MANUFACTURED INTEGRATED CIRCUITS, AND RELATED METHODS
    85.
    发明申请
    TIE-OFF STRUCTURES FOR MIDDLE-OF-LINE (MOL) MANUFACTURED INTEGRATED CIRCUITS, AND RELATED METHODS 审中-公开
    中间线（MOL）制造集成电路的TIE-OFF结构及相关方法

    公开(公告)号：US20160079167A1

    公开(公告)日：2016-03-17

    申请号：US14484353

    申请日：2014-09-12

    Applicant: QUALCOMM Incorporated

    Inventor： John Jianhong Zhu ,  Kern Rim ,  Stanley Seungchul Song ,  Jeffrey Junhao Xu

    IPC: H01L23/535 ,  H01L21/768 ,  H01L27/06

    CPC classification number: H01L23/535 ,  H01L21/76895 ,  H01L27/0207 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Tie-off structures for middle-of-line (MOL) manufactured integrated circuits, and related methods are disclosed. As a non-limiting example, the tie-off structure may be used to tie-off a drain or source of a transistor to the gate of the transistor, such as provided in a dummy gate used for isolation purposes. In this regard in one aspect, a MOL stack is provided that includes a metal gate connection that is coupled to a metal layer through metal structure disposed in and above a dielectric layer above a gate associated with the metal gate connection. By coupling the metal gate connection to the metal layer, the gate of a transistor may be coupled or “tied-off” to a source or drain element of the transistor. This may avoid the need to etch the metal gate connection provided below the dielectric layer to provide sufficient connectivity between the metal layer and the metal gate connection.

    Abstract translation: 公布了中线（MOL）制造集成电路的结合结构及相关方法。 作为非限制性示例，可以使用结合结构将晶体管的漏极或源极结合到晶体管的栅极，例如在用于隔离目的的虚拟栅极中提供。 在这方面，在一方面，提供了一种MOL堆叠，其包括金属栅极连接，金属栅极连接通过设置在与金属栅极连接相关联的栅极上方的电介质层中和上方的金属结构耦合到金属层。 通过将金属栅极连接耦合到金属层，晶体管的栅极可以耦合或“截止”到晶体管的源极或漏极元件。 这可以避免需要蚀刻在介电层下方提供的金属栅极连接，以在金属层和金属栅极连接之间提供足够的连通性。

    Via material selection and processing
    87.
    发明授权
    Via material selection and processing 有权
    通过材料选择和处理

    公开(公告)号：US09196583B1

    公开(公告)日：2015-11-24

    申请号：US14274470

    申请日：2014-05-09

    Applicant: QUALCOMM Incorporated

    Inventor： John Jianhong Zhu ,  Jeffrey Junhao Xu ,  Stanley Seungchul Song ,  Kern Rim ,  Zhongze Wang

    IPC: H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

    CPC classification number: H01L23/5226 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76879 ,  H01L23/5228 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Semiconductor interconnects and methods for making semiconductor interconnects. An interconnect may include a first via of a first conductive material between a first conductive interconnect layer and a first middle of line (MOL) interconnect layer. The first MOL interconnect layer is on a first level. The first via is fabricated with a single damascene process. Such a semiconductor interconnect also includes a second via of a second conductive material between the first conductive interconnect layer and a second MOL interconnect layer. The second MOL interconnect layer is on a second level. The second via is fabricated with a dual damascene process. The first conductive material is different than the second conductive material.

    Abstract translation: 用于半导体互连的半导体互连和方法。 互连可以包括在第一导电互连层和第一中间线（MOL）互连层之间的第一导电材料的第一通孔。 第一个MOL互连层位于第一层。 第一个通孔用单个镶嵌工艺制造。 这种半导体互连还包括在第一导电互连层和第二MOL互连层之间的第二导电材料的第二通孔。 第二个MOL互连层位于第二层。 第二个通孔用双镶嵌工艺制造。 第一导电材料与第二导电材料不同。

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