公开(公告)号：US20220108742A1

公开(公告)日：2022-04-07

申请号：US17062148

申请日：2020-10-02

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Zhongze WANG ,  Xiaonan CHEN ,  Xiaochun ZHU

IPC: G11C11/4094 ,  G11C11/4091 ,  G11C11/4099 ,  G11C11/404 ,  G11C5/06

Abstract: Certain aspects of the present disclosure provide a circuit for in-memory computation. The circuit generally includes a memory cell having a bit-line and a complementary bit-line, a first capacitive element coupled to the bit-line, a second capacitive element coupled to the complementary bit-line, a processing circuit, a first switch coupled between a first input of the processing circuit and the bit-line, and a second switch coupled between a second input of the processing circuit and the complementary bit-line

公开(公告)号：US20220013522A1

公开(公告)日：2022-01-13

申请号：US16924757

申请日：2020-07-09

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Bin YANG ,  Haining YANG

IPC: H01L27/092 ,  H01L23/528 ,  H01L29/66 ,  H01L21/8234

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device with buried rails (e.g., buried power and ground rails). One example semiconductor device generally includes a substrate; a first rail, wherein a portion of the first rail is disposed in the substrate, the portion of the first rail having a first width greater than a second width of another portion of the first rail; a second rail, wherein a portion of the second rail is disposed in the substrate, the portion of the second rail having a third width greater than a fourth width of another portion of the second rail; and one or more transistors disposed above the substrate and between the first rail and the second rail.

公开(公告)号：US20210398972A1

公开(公告)日：2021-12-23

申请号：US16908126

申请日：2020-06-22

Applicant: QUALCOMM Incorporated

Inventor： Bin YANG ,  Haining YANG ,  Xia LI ,  Kwanyong LIM

IPC: H01L27/06 ,  H01L29/423 ,  H01L29/737 ,  H01L29/786 ,  H01L21/8249 ,  H01L29/10 ,  H01L29/08

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device with a heterojunction bipolar transistor (HBT) integrated with a gate-all-around (GAA) transistor. One example semiconductor device generally includes a first substrate, a second substrate adjacent to the first substrate, a GAA transistor disposed above the first substrate, and a HBT disposed above the second substrate. Other aspects of the present disclosure generally relate to a method for fabricating a semiconductor device. An exemplary fabrication method generally comprises forming a GAA transistor disposed above a first substrate and forming a HBT disposed above a second substrate, wherein the second substrate is adjacent to the first substrate.

公开(公告)号：US20210134343A1

公开(公告)日：2021-05-06

申请号：US16672722

申请日：2019-11-04

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Jianguo YAO ,  Bin YANG

IPC: G11C11/40 ,  G11C11/54 ,  G06F9/30 ,  G06N3/063

Abstract: Certain aspects provide methods and apparatus for in-memory convolution computation. An example circuit for such computation generally includes a memory cell having a bit-line and a complementary bit-line and a computation circuit coupled to a computation input node of the circuit and at least one of the bit-line or the complementary bit-line. In certain aspects, the computation circuit comprises a counter, an NMOS transistor coupled to the memory cell, and a PMOS transistor coupled to the memory cell, drains of the NMOS and PMOS transistors being coupled to the counter.

公开(公告)号：US20210036120A1

公开(公告)日：2021-02-04

申请号：US16526756

申请日：2019-07-30

Applicant: QUALCOMM Incorporated

Inventor： Bin YANG ,  Haining YANG ,  Xia LI

IPC: H01L29/423 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/762

Abstract: A semiconductor device is disclosed that includes a plurality of fins on a substrate. A long channel gate is disposed over a first portion of the plurality of fins. A gate contact is provided having an extended portion that extends into an active area from a gate contact base outside the active area.

公开(公告)号：US20200350124A1

公开(公告)日：2020-11-05

申请号：US16748775

申请日：2020-01-21

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Bin YANG ,  Kai LIU

IPC: H01G4/30 ,  H01L49/02 ,  H01G4/33 ,  H01G4/012

Abstract: Planarization of the M1 metal layer reduces surface roughness and fills in pin-holes for a more reliable capacitor. For example, a MIM capacitor on a glass substrate may begin with patterning of the M1 layer, deposition of a planarization material, etch back the planarization material to planarize the M1 surface and fill in any pits/pin-holes. In addition, multiple-cycles of deposit and etch back further reduce M1 surface roughness and fill in possible pin-holes to acceptable level.

公开(公告)号：US20200259004A1

公开(公告)日：2020-08-13

申请号：US16274094

申请日：2019-02-12

Applicant: QUALCOMM Incorporated

Inventor： Gengming TAO ,  Bin YANG ,  Xia LI

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/40 ,  H01L29/66 ,  H01L29/205

Abstract: Power amplifiers in radio frequency circuits are typically implemented as heterojunction bipolar transistors. In applications such as in 5G systems, the circuits are expected to operate at very high speeds, e.g., up to 100 GHz. Also, a certain amount of output power should be maintained for stable operation. To achieve both high power and high speed, it is proposed to incorporate field plates in the heterojunction bipolar transistors to reduce electric field in the collector. This allows the breakdown voltage of the transistor to be high, which aids in power output. At the same time, the collector can be relatively thin, which aids in operation speed.

公开(公告)号：US20200052103A1

公开(公告)日：2020-02-13

申请号：US16058388

申请日：2018-08-08

Applicant: QUALCOMM Incorporated

Inventor： Gengming TAO ,  Bin YANG ,  Xia LI

IPC: H01L29/778 ,  H01L29/06 ,  H01L29/66

Abstract: Certain aspects of the present disclosure provide a high electron mobility transistor (HEMT). The HEMT generally includes a gallium nitride (GaN) layer and an aluminum gallium nitride (AlGaN) layer disposed above the GaN layer. The HEMT also includes a source electrode, a gate electrode, and a drain electrode disposed above the AlGaN layer. The HEMT further includes n-doped protuberance(s) disposed above the AlGaN layer and disposed between at least one of: the gate electrode and the drain electrode; or the source electrode and the gate electrode. Each of the n-doped protuberances is separated from the gate electrode, the drain electrode, and the source electrode.

公开(公告)号：US20190385947A1

公开(公告)日：2019-12-19

申请号：US16007921

申请日：2018-06-13

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Junjing BAO ,  Bin YANG ,  Gengming TAO

IPC: H01L23/522 ,  H01L49/02 ,  H01L23/528 ,  H01L23/66

Abstract: A capacitor includes a first set of conductive fingers having a first conductive pitch at a first interconnect layer and arranged in a first unidirectional routing. The capacitor further includes a second set of conductive fingers having a second conductive pitch at a second interconnect layer and arranged in a second unidirectional routing that is orthogonal to the first unidirectional routing. The first conductive pitch is different from the second conductive pitch. A first set of through finger vias electrically couples the first set of conductive fingers of the first interconnect layer to the second set of conductive fingers of the second interconnect layer. A third set of conductive fingers at a third conductive layer are parallel to, but offset from, the first set of conductive fingers. A second set of through finger vias electrically couples the third set of conductive fingers to the second set of conductive fingers.

公开(公告)号：US20190312153A1

公开(公告)日：2019-10-10

申请号：US15947667

申请日：2018-04-06

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Bin YANG ,  Gengming TAO

IPC: H01L29/93 ,  H01L27/08 ,  H01L29/06 ,  H01L29/94 ,  H01L29/739 ,  H01G7/06

Abstract: Aspects of the present disclosure provide semiconductor variable capacitor devices. In one embodiment, a semiconductor variable capacitor includes a gate oxide layer comprising a first layer portion with a first thickness and a second layer portion with a second thickness; a first non-insulative region disposed above the gate oxide layer; a first semiconductor region disposed beneath the gate oxide layer; a second semiconductor region disposed beneath the gate oxide layer and adjacent to the first semiconductor region, wherein the second semiconductor region comprises a different doping type than the first semiconductor region a second non-insulative region coupled to the first semiconductor region; and a control terminal coupled to a control region coupled to the second semiconductor region such that a first capacitance between the first non-insulative region and the second non-insulative region is configured to be adjusted by varying a control voltage applied to the control region.