公开(公告)号：US08787090B2

公开(公告)日：2014-07-22

申请号：US13372669

申请日：2012-02-14

申请人： Akira Goda ,  Seiichi Aritome

发明人： Akira Goda ,  Seiichi Aritome

IPC分类号： G11C11/34

CPC分类号： G11C16/3468

摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for programming memory cells. One method includes determining a quantity of erase pulses used to place a group of memory cells of the array in an erased state, and adjusting at least one operating parameter associated with programming the group of memory cells at least partially based on the determined quantity of erase pulses.

摘要翻译： 本公开的实施例提供用于编程存储器单元的方法，设备，模块和系统。 一种方法包括确定用于将阵列的一组存储器单元放置在擦除状态中的擦除脉冲的量，以及至少部分地基于确定的擦除量来调整与编程存储器单元组相关联的至少一个操作参数 脉冲。

公开(公告)号：US08536634B2

公开(公告)日：2013-09-17

申请号：US13213971

申请日：2011-08-19

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： H01L23/00

CPC分类号： H01L27/105 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11534 ,  H01L27/11546 ,  H01L29/42336 ,  H01L29/7881 ,  H01L2924/0002 ,  H01L2924/00

摘要： Method and device embodiments are described for fabricating MOSFET transistors in a semiconductor also containing non-volatile floating gate transistors. MOSFET transistor gate dielectric smiling, or bird's beaks, are adjustable by re-oxidation processing. An additional re-oxidation process is performed by opening a poly-silicon layer prior to forming an inter-poly oxide dielectric provided for the floating gate transistors.

公开(公告)号：US08493792B2

公开(公告)日：2013-07-23

申请号：US13309760

申请日：2011-12-02

申请人： Seiichi Aritome ,  Soo Jin Wi

发明人： Seiichi Aritome ,  Soo Jin Wi

IPC分类号： G11C16/06 ,  G11C11/56

CPC分类号： G11C11/5628 ,  G11C16/12 ,  G11C16/3418 ,  G11C16/349

摘要： A programming method includes setting the voltages of bit lines, performing a program operation, performing a program verify operation by supplying a program verify voltage and determining whether all of the memory cells of the selected page have been programmed with a target threshold voltage or higher, counting the number of passed memory cells corresponding to a number of pass bits, if, a result of the program verify operation, the program operation failed to program all of the memory cells of the selected page to the target threshold voltage or higher, and making a determination that determines whether the number of pass bits is greater than the first number of pass permission bits, and raising a voltage of a bit line coupled to a failed memory cell, if, as a result of the determination, the number of pass bits is greater than the first number of pass permission bits.

摘要翻译： 一种编程方法，包括设置位线的电压，执行编程操作，通过提供编程验证电压并确定所选择的页面的所有存储单元是否已经被编程为目标阈值电压或更高，执行编程验证操作， 对与多个通过位相对应的经过的存储单元的数量进行计数，如果程序验证操作的结果，程序操作不能将所选页的所有存储单元编程为目标阈值电压或更高，并且使 确定通过位的数量是否大于第一数量的通过许可位，并且提高耦合到故障存储器单元的位线的电压，如果作为确定的结果，通过位的数量 大于第一个通过许可位数。

公开(公告)号：US08446011B2

公开(公告)日：2013-05-21

申请号：US13243510

申请日：2011-09-23

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L27/11519 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： Each of the first bit lines of a device has an upper surface and a lower surface, with the upper surface being more outwardly located over a semiconductor surface than the lower surface. A second bit line of the device has an upper surface and a lower surface, with the upper surface thereof being more outwardly located over the semiconductor surface than the lower surface. The upper surface of the second bit line is more outwardly located over the semiconductor surface than the upper surfaces of the first bit lines. The first bit lines are each adjacent to the second bit line and the second bit line is configured to be selectively coupled to a memory cell other than memory cells to which the first bit lines are configured to be selectively coupled. The second bit line does not overlap any of the first bit lines.

摘要翻译： 装置的每个第一位线具有上表面和下表面，其中上表面比下表面更向外位于半导体表面之上。 器件的第二位线具有上表面和下表面，其上表面比下表面更向外位于半导体表面之上。 第二位线的上表面比第一位线的上表面更向外位于半导体表面之上。 第一位线各自与第二位线相邻，并且第二位线被配置为选择性地耦合到除了​​第一位线被配置为选择性耦合的存储器单元之外的存储器单元。 第二位线不与第一位线重叠。

公开(公告)号：US08415223B2

公开(公告)日：2013-04-09

申请号：US13365472

申请日：2012-02-03

申请人： Kirk D. Prall ,  Behnam Moradi ,  Seiichi Aritome ,  Di Li ,  Chris Larsen

发明人： Kirk D. Prall ,  Behnam Moradi ,  Seiichi Aritome ,  Di Li ,  Chris Larsen

IPC分类号： H01L21/336

CPC分类号： H01L29/66825 ,  H01L21/22 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/324 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/788

摘要： Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.

公开(公告)号：US20130010547A1

公开(公告)日：2013-01-10

申请号：US13542372

申请日：2012-07-05

申请人： Seiichi ARITOME

发明人： Seiichi ARITOME

IPC分类号： G11C7/06

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/3427

摘要： A method of operating a semiconductor device includes programming selected memory cells by supplying a selected word line with a program voltage which increases and supplying the remaining unselected word lines with a first pass voltage which is substantially constant; and programming the selected memory cells while supplying first unselected word lines adjacent to the selected word line with a second pass voltage increasing in proportion to the program voltage, when a difference between the program voltage and the first pass voltage reaches a critical voltage difference.

摘要翻译： 一种操作半导体器件的方法包括通过向所选择的字线提供编程电压来对选定的存储器单元进行编程，所述编程电压增加并提供剩余的未选择字线，所述第一通过电压基本上是恒定的; 以及当所述编程电压和所述第一通过电压之间的差达到临界电压差时，以与所述编程电压成比例的方式增加的第二通过电压来提供与所述选定字线相邻的第一未选字线。

公开(公告)号：US20120307565A1

公开(公告)日：2012-12-06

申请号：US13353429

申请日：2012-01-19

申请人： Seiichi ARITOME

发明人： Seiichi ARITOME

IPC分类号： G11C16/10 ,  G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/3409

摘要： A method for operating a non-volatile memory device includes performing an erase operation onto a memory block including a plurality of memory cells, and performing a first soft program operation onto all the memory cells of a string, after the erase operation, grouping word lines of the string into a plurality of word line groups, and performing a second soft program operation onto memory cells coupled with the word lines of each word line group.

摘要翻译： 一种用于操作非易失性存储器件的方法包括在包括多个存储器单元的存储器块上执行擦除操作，并且在擦除操作之后对字符串的所有存储单元执行第一软编程操作，将字线 并且对与每个字线组的字线耦合的存储器单元执行第二软编程操作。

公开(公告)号：US08305810B2

公开(公告)日：2012-11-06

申请号：US13164813

申请日：2011-06-21

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/3427 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： Multiple select gates in association with non-volatile memory cells are described. Various embodiments include multiple select gate structure, process, and operation and their applicability for memory devices, modules, and systems. In one embodiment a memory array is described. The memory array includes a number of select gates coupled in series to a number of non-volatile memory cells. A first select gate includes a control gate and a floating gate electrically connected together and a second select gate includes a control gate and a floating gate which are electrically separated by a dielectric layer.

摘要翻译： 描述与非易失性存储器单元相关联的多个选择门。 各种实施例包括多个选择栅极结构，工艺和操作及其对存储器件，模块和系统的适用性。 在一个实施例中描述了存储器阵列。 存储器阵列包括多个与多个非易失性存储器单元串联耦合的选择栅极。 第一选择栅极包括电连接在一起的控制栅极和浮置栅极，第二选择栅极包括由电介质层电隔离的控制栅极和浮置栅极。

公开(公告)号：US20120258574A1

公开(公告)日：2012-10-11

申请号：US13495287

申请日：2012-06-13

申请人： Akira GODA ,  Seiichi Aritome

发明人： Akira GODA ,  Seiichi Aritome

IPC分类号： H01L21/8239

CPC分类号： G11C7/02 ,  G11C7/1036 ,  H01L27/105 ,  H01L27/11517 ,  H01L27/11526

摘要： A memory device includes a first bit line coupled to a first source/drain region of a first multiplexer gate, a second bit line coupled to a first source/drain region of a second multiplexer gate, and a sensing device having an input coupled to a second source/drain region of the first multiplexer gate and a second source/drain region of the second multiplexer gate. The input of the sensing device is formed at a vertical level that is different than a vertical level at which at least one of the first and second bit lines is formed.

摘要翻译： 存储器件包括耦合到第一多路复用器门的第一源极/漏极区域的第一位线，耦合到第二多路复用器栅极的第一源极/漏极区域的第二位线以及耦合到第二多路复用器栅极的输入的感测器件 第一多路复用器栅极的第二源极/漏极区域和第二多路复用器栅极的第二源极/漏极区域。 感测装置的输入形成在与形成第一和第二位线中的至少一个的垂直电平不同的垂直电平处。

公开(公告)号：US08238167B2

公开(公告)日：2012-08-07

申请号：US13162633

申请日：2011-06-17

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： G11C16/04

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/349 ,  G11C2211/5644

摘要： The present disclosure includes various method, device, system, and module embodiments for memory cycle voltage adjustment. One such method embodiment includes counting a number of process cycles performed on a first memory block in a memory device. This method embodiment also includes adjusting at least one program voltage, from an initial program voltage to an adjusted voltage, in response to the counted number of process cycles.

摘要翻译： 本公开包括用于存储器周期电压调整的各种方法，装置，系统和模块实施例。 一种这样的方法实施例包括对在存储器件中的第一存储器块执行的处理循环的数量进行计数。 该方法实施例还包括响应于所计算的处理周期数，将至少一个编程电压从初始编程电压调整到调整的电压。