公开(公告)号：US10007486B2

公开(公告)日：2018-06-26

申请号：US12325982

申请日：2008-12-01

申请人： Harold B Noyes

发明人： Harold B Noyes

IPC分类号： G06F7/00 ,  G06F17/30 ,  G06F7/02 ,  G06F5/06

CPC分类号： G06F7/02 ,  G06F5/06 ,  G06F2207/025

摘要： Systems and methods are provided, such as those that enable identification of data flows and corresponding results in a pattern-recognition processor. In one embodiment, a system may include the pattern-recognition processor and a flow identification register, wherein a unique flow identifier for each data flow is stored in the register. The system may include a results buffer that stores the results data and the flow identifier for each data flow, so that the results data may be related to a specific data flow.

公开(公告)号：US09996489B2

公开(公告)日：2018-06-12

申请号：US14974349

申请日：2015-12-18

申请人： Huawei Technologies Co., Ltd.

发明人： Yaron Shachar ,  Yoav Peleg ,  Alex Tal ,  Alex Umansky ,  Rami Zemach ,  Lixia Xiong ,  Yuchun Lu

IPC分类号： G06F13/00 ,  G06F13/37 ,  G06F5/06 ,  G06F13/16 ,  G06F13/42

CPC分类号： G06F13/37 ,  G06F5/065 ,  G06F13/1673 ,  G06F13/4234

摘要： The invention relates to a memory aggregation device for storing a set of input data streams and retrieving data to a set of output data streams, the memory aggregation device comprising: a set of first-in first-out (FIFO) memories each comprising an input and an output; an input interconnector configured to interconnect each one of the set of input data streams to each input of the set of FIFO memories according to an input interconnection matrix; an output interconnector configured to interconnect each output of the set of FIFO memories to each one of the set of output data streams according to an output interconnection matrix; an input selector; an output selector; and a memory controller.

公开(公告)号：US20180113706A1

公开(公告)日：2018-04-26

申请号：US15790320

申请日：2017-10-23

申请人： DENSO CORPORATION

发明人： Bert BOEDDEKER ,  Dominik LANGEN ,  Sebastian KEHR

IPC分类号： G06F9/44 ,  G06F9/38 ,  G06F9/52 ,  G06F5/06

CPC分类号： G06F8/76 ,  G05B19/0421 ,  G06F5/06 ,  G06F9/38 ,  G06F9/5066 ,  G06F9/52 ,  G06F9/544 ,  G06F2209/5017

摘要： A method for porting an existing vehicle control software developed for a single-core control device into a modified multi-core control software or for converting an existing vehicle control software into an optimized multi-core control software is provided. The existing control software comprises numerous repeatedly executable runnables. Information is exchanged between the runnables through writing and reading of communication variables. A modified information exchange via time implicit communication is provided for parallelized runnables in the multi-core control software that is generated by the method. The method includes: analysis of the existing control software regarding a writer-to-reader cardinality of the information exchange with respect to a communication variable; and defining an implementation of the time implicit communication as a function of the determined writer-to-reader cardinality.

公开(公告)号：US20180081625A1

公开(公告)日：2018-03-22

申请号：US15271077

申请日：2016-09-20

申请人： Advanced Micro Devices, Inc.

发明人： XuHong Xiong ,  Pingping Shao ,  ZhongXiang Luo ,  ChenBin Wang

IPC分类号： G06F5/14 ,  G11C21/00 ,  G06F12/0811 ,  G06F13/16 ,  G06F5/06

CPC分类号： G06F5/14 ,  G06F5/065 ,  G06F12/0811 ,  G06F13/1673 ,  G06F2205/067 ,  G06F2205/126 ,  G06F2212/283 ,  G11C21/00

摘要： A system and method for managing data in a ring buffer is disclosed. The system includes a legacy ring buffer functioning as an on-chip ring buffer, a supplemental buffer for storing data in the ring buffer, a preload ring buffer that is on-chip and capable of receiving preload data from the supplemental buffer, a write controller that determines where to write data that is write requested by a write client of the ring buffer, and a read controller that controls a return of data to a read client pursuant to a read request to the ring buffer.

公开(公告)号：US09917787B2

公开(公告)日：2018-03-13

申请号：US15184375

申请日：2016-06-16

申请人： Intel Corporation

发明人： Todd Rimmer ,  Thomas D. Lovett ,  Albert Cheng

IPC分类号： H04L12/801 ,  H04L12/919 ,  H04L12/925 ,  H04L12/933 ,  H04L12/861 ,  G06F13/42 ,  H04L12/931 ,  H04L12/851 ,  G06F5/06 ,  G06F13/16

CPC分类号： H04L47/39 ,  G06F5/065 ,  G06F13/1673 ,  G06F13/4221 ,  G06F2205/067 ,  H04L47/2408 ,  H04L47/2433 ,  H04L47/245 ,  H04L47/30 ,  H04L47/722 ,  H04L47/765 ,  H04L49/103 ,  H04L49/109 ,  H04L49/358 ,  H04L49/505 ,  H04L49/70 ,  H04L49/9057

摘要： Method, apparatus, and systems for implementing flexible credit exchange within high performance fabrics. Available buffer space in a receive buffer on a receive-side of a link is managed and tracked at the transmit-side of the link using credits. Peer link interfaces coupled via a link are provided with receive buffer configuration information that specifies how the receive buffer space in each peer is partitioned and space allocated for each buffer, including a plurality of virtual lane (VL) buffers. Credits are used for tracking buffer space consumption and in credits are returned from the receive-side indicating freed buffer space. The peer link interfaces exchange credit organization information to inform the other peer of how much space each credit represents. In connection with data transfer over the link, the transmit-side de-allocates credits based on an amount of buffer space to be consumed in applicable buffers in the receive buffer. Upon space being freed in the receive buffer, the receive-side returns credit ACKnowledgements (ACKs) identifying a VL for which space has been freed.

公开(公告)号：US20180039593A1

公开(公告)日：2018-02-08

申请号：US15784607

申请日：2017-10-16

申请人： Intel Corporation

发明人： Mark Debbage ,  Yatin M. Mutha

IPC分类号： G06F13/372 ,  G06F13/16 ,  G06F13/362 ,  G06F5/06 ,  G06F13/42 ,  G06F13/28 ,  G06F15/78

CPC分类号： G06F13/372 ,  G06F5/065 ,  G06F13/128 ,  G06F13/1673 ,  G06F13/28 ,  G06F13/3625 ,  G06F13/4221 ,  G06F13/4265 ,  G06F13/4282 ,  G06F15/167 ,  G06F15/7807 ,  G06F2205/067 ,  G06F2213/0026 ,  G06F2213/2806 ,  G06F2213/36

摘要： Method and apparatus for implementing an optimized credit return mechanism for packet sends. A Programmed Input/Output (PIO) send memory is partitioned into a plurality of send contexts, each comprising a memory buffer including a plurality of send blocks configured to store packet data. A storage scheme using FIFO semantics is implemented with each send block associated with a respective FIFO slot. In response to receiving packet data written to the send blocks and detecting the data in those send blocks has egressed from a send context, corresponding freed FIFO slots are detected, and a lowest slot for which credit return indicia has not be returned is determined. The highest slot in a sequence of freed slots from the lowest slot is then determined, and corresponding credit return indicia is returned. In one embodiment an absolute credit return count is implemented for each send context, with an associated absolute credit sent count tracked via software that writes to the PIO send memory, with the two absolute credit counts used for flow control.

公开(公告)号：US20180024948A1

公开(公告)日：2018-01-25

申请号：US15458561

申请日：2017-03-14

申请人： SANDISK TECHNOLOGIES LLC

发明人： Wanfang Tsai ,  Yan Li

IPC分类号： G06F13/16 ,  G06F5/06 ,  G11C16/34 ,  G06F3/06 ,  G11C16/04 ,  G11C16/10

CPC分类号： G06F13/1673 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G06F5/065 ,  G06F13/1642 ,  G06F2205/067 ,  G06F2212/2022 ,  G06F2212/7203 ,  G11C7/1039 ,  G11C7/106 ,  G11C7/1066 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427 ,  G11C16/3436 ,  G11C16/3454 ,  G11C29/84

摘要： Systems and methods for controlling data flow and data alignment using data expand and compress circuitry arranged between a variable data rate bi-directional first in, first out (FIFO) buffer and one or more memory arrays to compensate for bad column locations within the one or more memory arrays are described. The bi-directional FIFO may have a variable data rate with the array side and a fixed data rate with a serializer/deserializer (SERDES) circuit that drives input/output (I/O) circuitry. The data expand and compress circuitry may pack and unpack data and then align the data passing between the one or more memory arrays and the bi-directional FIFO using a temporary buffer, data shuffling logic, and selective pipeline stalls.

公开(公告)号：US09824056B2

公开(公告)日：2017-11-21

申请号：US13503702

申请日：2010-10-29

申请人： Yuanlong Wang

发明人： Yuanlong Wang

IPC分类号： G06F1/04 ,  G06F1/12 ,  G06F5/06 ,  G06F13/42 ,  G06F1/32

CPC分类号： G06F13/4243 ,  G06F1/3206 ,  G06F1/3237 ,  G06F1/3275 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： The timing of the synchronous interface is controlled by a dock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.

公开(公告)号：US20170322767A1

公开(公告)日：2017-11-09

申请号：US15148325

申请日：2016-05-06

申请人： Texas Instruments Incorporated

发明人： Shailesh Ganapat Ghotgalkar

IPC分类号： G06F5/14 ,  G06F3/06 ,  G06F5/06

CPC分类号： G06F5/14 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0673 ,  G06F5/065 ,  G06F2205/067 ,  G06F2205/126

摘要： A system, method and computer readable medium for operating a First In, First Out (FIFO) buffer that transfers data between a host and a plurality of endpoints using chip select is disclosed. The method includes receiving a current value of a read pointer and a status for an active endpoint and reading data at a location to which the read pointer points and setting a tag associated with the location to which the read pointer points to indicate availability.

公开(公告)号：US20170317862A1

公开(公告)日：2017-11-02

申请号：US15651364

申请日：2017-07-17

申请人： ATI Technologies ULC

发明人： Andy Sung ,  Leon Lai ,  Daniel Wang

IPC分类号： H04L27/00 ,  H04L7/00 ,  G06F5/06

CPC分类号： H04L27/00 ,  G06F5/06 ,  H04L7/005

摘要： A method and system is provided for allowing signals across electrical domains. The method includes applying a clock signal (of at least 1 GHz) to an electronic element in a location having first electrical properties. Data is output from the first electronic element; and received at a second electronic element located in a location having second electrical properties. The first and second electrical properties are different by either voltage and clock frequency.