公开(公告)号：US20110201163A1

公开(公告)日：2011-08-18

申请号：US13041740

申请日：2011-03-07

Applicant: Joerg Appenzeller ,  Supratik Guha ,  Emanuel Tutuc

Inventor： Joerg Appenzeller ,  Supratik Guha ,  Emanuel Tutuc

IPC: H01L21/336 ,  H01L21/20

CPC classification number: H01L21/30604 ,  B82Y10/00 ,  H01L21/02603 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/1041 ,  H01L29/125 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/78696

Abstract: A semiconductor structure is provided, which includes multiple sections arranged along a longitudinal axis. Preferably, the semiconductor structure comprises a middle section and two terminal sections located at opposite ends of the middle section. A semiconductor core having a first dopant concentration preferably extends along the longitudinal axis through the middle section and the two terminal sections. A semiconductor shell having a second, higher dopant concentration preferably encircles a portion of the semiconductor core at the two terminal sections, but not at the middle section, of the semiconductor structure. It is particularly preferred that the semiconductor structure is a nanostructure having a cross-sectional dimension of not more than 100 nm.

Abstract translation: 提供了一种半导体结构，其包括沿纵向轴线布置的多个部分。 优选地，半导体结构包括位于中间部分的相对端的中间部分和两个端子部分。 具有第一掺杂剂浓度的半导体芯片优选地沿着纵向轴线延伸通过中间部分和两个端子部分。 具有第二较高掺杂剂浓度的半导体壳体优选地环绕半导体结构的两个端子部分但不在中间部分处的半导体芯体的一部分。 特别优选的是，半导体结构是具有不大于100nm的横截面尺寸的纳米结构。

公开(公告)号：US07820502B2

公开(公告)日：2010-10-26

申请号：US11926627

申请日：2007-10-29

Applicant: Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaolav Horak ,  Charles William Koburger, III ,  Peter H. Mitchell ,  Larry Alan Nesbit

Inventor： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaolav Horak ,  Charles William Koburger, III ,  Peter H. Mitchell ,  Larry Alan Nesbit

IPC: H01L21/8238

CPC classification number: H01L51/057 ,  B82Y10/00 ,  G11C13/025 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/125 ,  H01L29/66409 ,  H01L29/772 ,  H01L51/0048 ,  Y10S977/734

Abstract: A method for forming carbon nanotube field effect transistors, arrays of carbon nanotube field effect transistors, and device structures and arrays of device structures formed by the methods. The methods include forming a stacked structure including a gate electrode layer and catalyst pads each coupled electrically with a source/drain contact. The gate electrode layer is divided into multiple gate electrodes and at least one semiconducting carbon nanotube is synthesized by a chemical vapor deposition process on each of the catalyst pads. The completed device structure includes a gate electrode with a sidewall covered by a gate dielectric and at least one semiconducting carbon nanotube adjacent to the sidewall of the gate electrode. Source/drain contacts are electrically coupled with opposite ends of the semiconducting carbon nanotube to complete the device structure. Multiple device structures may be configured either as a memory circuit or as a logic circuit.

Abstract translation: 一种形成碳纳米管场效应晶体管的方法，碳纳米管场效应晶体管的阵列，以及通过该方法形成的器件结构和器件结构阵列。 所述方法包括形成包括栅极电极层和各个与源极/漏极接触电连接的催化剂焊盘的堆叠结构。 栅极电极层被分成多个栅极电极，并且通过化学气相沉积工艺在每个催化剂焊盘上合成至少一个半导体碳纳米管。 完成的器件结构包括具有由栅极电介质覆盖的侧壁的栅电极和与栅电极的侧壁相邻的至少一个半导体碳纳米管。 源极/漏极触点与半导体碳纳米管的相对端电耦合以完成器件结构。 多个器件结构可以被配置为存储器电路或逻辑电路。

公开(公告)号：US20100072460A1

公开(公告)日：2010-03-25

申请号：US12564091

申请日：2009-09-22

Applicant: Mikael T. Bjoerk ,  Joachim Knoch ,  Heike E. Riel ,  Walter Heinrich Riess ,  Heinz Schmid

Inventor： Mikael T. Bjoerk ,  Joachim Knoch ,  Heike E. Riel ,  Walter Heinrich Riess ,  Heinz Schmid

IPC: H01L29/775 ,  H01L29/12 ,  H01L21/335

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/125 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78642 ,  H01L29/78696 ,  H01L2924/0002 ,  Y10S977/762 ,  H01L2924/00

Abstract: An electronic device and method of manufacturing the device. The device includes a semiconducting region, which can be a nanowire, a first contact electrically coupled to the semiconducting region, and at least one second contact capacitively coupled to the semiconducting region. At least a portion of the semiconducting region between the first contact and the second contact is covered with a dipole layer. The dipole layer can act as a local gate on the semiconducting region to enhance the electric properties of the device.

Abstract translation: 电子装置及其制造方法。 器件包括半导体区域，其可以是纳米线，电耦合到半导体区域的第一接触点和电容耦合到半导体区域的至少一个第二接触点。 第一触点和第二触点之间的半导体区域的至少一部分被偶极子层覆盖。 偶极层可以用作半导体区域上的局部栅极，以增强器件的电性能。

公开(公告)号：US20100072455A1

公开(公告)日：2010-03-25

申请号：US12235359

申请日：2008-09-22

Applicant: Mark Albert Crowder

Inventor： Mark Albert Crowder

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/125 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/78 ,  Y10S977/936

Abstract: A well-structure anti-punch-through microwire device and associated fabrication method are provided. The method initially forms a microwire with alternating highly and lightly doped cylindrical regions. A channel ring is formed external to the microwire outer shell and surrounding a first dopant well-structure region in the microwire, between source and drain (S/D) regions of the microwire. The S/D regions are doped with a second dopant, opposite to the first dopant. A gate dielectric ring is formed surrounding the channel ring, and a gate electrode ring is formed surrounding the gate dielectric ring. The well-structure, in contrast to conventional micro or nanowire transistors, helps prevent the punch-through phenomena.

Abstract translation: 提供了良好结构的抗穿通微线器件和相关的制造方法。 该方法最初形成具有交替的高度和轻掺杂的圆柱形区域的微线。 通道环形成在微线外壳的外部，并且包围微线中的微线的源极和漏极（S / D）区域之间的第一掺杂剂阱结构区域。 S / D区域掺杂有与第一掺杂剂相反的第二掺杂剂。 围绕通道环形成栅介质环，并且围绕栅介质环形成栅电极环。 与传统的微纳米线或纳米线晶体管相反，井结构有助于防止穿透现象。

公开(公告)号：US07344961B2

公开(公告)日：2008-03-18

申请号：US11117702

申请日：2005-04-29

Applicant: Linda T. Romano ,  James M. Hamilton

Inventor： Linda T. Romano ,  James M. Hamilton

IPC: H01L21/302

CPC classification number: C30B29/605 ,  B82Y10/00 ,  C30B11/12 ,  H01L21/02439 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/02606 ,  H01L21/02639 ,  H01L21/02645 ,  H01L21/02653 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/125 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/78684 ,  H01L29/7869 ,  H01L29/78696 ,  H01L51/0048 ,  Y10S977/762 ,  Y10S977/938 ,  Y10T428/139 ,  Y10T428/2902 ,  Y10T428/2949

Abstract: The present invention is directed to methods to produce, process, and exploit nanomaterials, and particularly elongated nanowire materials. The invention provides a method for producing nanowires that includes providing a thin film of a catalyst material with varying thickness on a substrate, heating the substrate and thin film, such that the thin film disassociates at the relatively thinner regions and vapor depositing a semiconductor onto the substrate to produce nanowires. A method is also provided in which two or more thin films of different materials are overlayed over a substrate, selectively etching the first underlying thin film to create a plurality of islands of the second thin film that mask portions of the first thin film and expose other portions and growing nanowires on the first thin film. Additional methods for producing nanowires are provided.

Abstract translation: 本发明涉及生产，加工和利用纳米材料，特别是细长的纳米线材料的方法。 本发明提供一种纳米线的制造方法，其包括在基板上提供具有变化的厚度的催化剂材料的薄膜，加热基板和薄膜，使得薄膜在相对较薄的区域分离并将半导体蒸镀到 底物产生纳米线。 还提供了一种方法，其中两个或更多个不同材料的薄膜覆盖在衬底上，选择性地蚀刻第一下面的薄膜以产生第二薄膜的多个岛，该第二薄膜的掩模部分的第一薄膜并暴露其他 部分和在第一薄膜上生长纳米线。 提供了生产纳米线的附加方法。

公开(公告)号：US20070281156A1

公开(公告)日：2007-12-06

申请号：US11386080

申请日：2006-03-21

Applicant: Charles Lieber ,  Xiangfeng Duan ,  Yi Cui ,  Yu Huang ,  Mark Gudiksen ,  Lincoln Lauhon ,  Jianfang Wang ,  Hongkun Park ,  Qingqiao Wei ,  Wenjie Liang ,  David Smith ,  Deli Wang ,  Zhaohui Zhong

Inventor： Charles Lieber ,  Xiangfeng Duan ,  Yi Cui ,  Yu Huang ,  Mark Gudiksen ,  Lincoln Lauhon ,  Jianfang Wang ,  Hongkun Park ,  Qingqiao Wei ,  Wenjie Liang ,  David Smith ,  Deli Wang ,  Zhaohui Zhong

IPC: D02G3/00

CPC classification number: G11C13/025 ,  B82Y10/00 ,  B82Y15/00 ,  B82Y30/00 ,  C30B11/00 ,  C30B25/00 ,  C30B25/005 ,  C30B29/60 ,  C30B29/605 ,  G01N27/4146 ,  G01N33/54373 ,  G11C11/56 ,  G11C13/0014 ,  G11C13/0019 ,  G11C13/04 ,  G11C2213/17 ,  G11C2213/18 ,  G11C2213/77 ,  G11C2213/81 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02557 ,  H01L21/0256 ,  H01L21/02603 ,  H01L21/02617 ,  H01L21/02628 ,  H01L21/02645 ,  H01L21/02653 ,  H01L23/53276 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/125 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/267 ,  H01L29/73 ,  H01L29/7781 ,  H01L29/78696 ,  H01L29/861 ,  H01L29/868 ,  H01L31/0352 ,  H01L31/08 ,  H01L33/18 ,  H01L51/0048 ,  H01L51/0595 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/3011 ,  Y02E10/549 ,  Y10S977/936 ,  Y10S977/938 ,  Y10S977/958 ,  Y10T428/2929 ,  Y10T428/298 ,  H01L2924/00

Abstract: The present invention relates generally to sub-microelectronic circuitry, and more particularly to nanometer-scale articles, including nanoscale wires which can be selectively doped at various locations and at various levels. In some cases, the articles may be single crystals. The nanoscale wires can be doped, for example, differentially along their length, or radially, and either in terms of identity of dopant, concentration of dopant, or both. This may be used to provide both n-type and p-type conductivity in a single item, or in different items in close proximity to each other, such as in a crossbar array. The fabrication and growth of such articles is described, and the arrangement of such articles to fabricate electronic, optoelectronic, or spintronic devices and components. For example, semiconductor materials can be doped to form n-type and p-type semiconductor regions for making a variety of devices such as field effect transistors, bipolar transistors, complementary inverters, tunnel diodes, light emitting diodes, sensors, and the like.

公开(公告)号：US07301199B2

公开(公告)日：2007-11-27

申请号：US10196337

申请日：2002-07-16

Applicant: Charles M. Lieber ,  Xiangfeng Duan ,  Yi Cui ,  Yu Huang ,  Mark Gudiksen ,  Lincoln J. Lauhon ,  Jianfang Wang ,  Hongkun Park ,  Qingqiao Wei ,  Wenjie Liang ,  David C. Smith ,  Deli Wang ,  Zhaohui Zhong

Inventor： Charles M. Lieber ,  Xiangfeng Duan ,  Yi Cui ,  Yu Huang ,  Mark Gudiksen ,  Lincoln J. Lauhon ,  Jianfang Wang ,  Hongkun Park ,  Qingqiao Wei ,  Wenjie Liang ,  David C. Smith ,  Deli Wang ,  Zhaohui Zhong

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/06

CPC classification number: G11C13/025 ,  B82Y10/00 ,  B82Y15/00 ,  B82Y30/00 ,  C30B11/00 ,  C30B25/00 ,  C30B25/005 ,  C30B29/60 ,  C30B29/605 ,  G01N27/4146 ,  G01N33/54373 ,  G11C11/56 ,  G11C13/0014 ,  G11C13/0019 ,  G11C13/04 ,  G11C2213/17 ,  G11C2213/18 ,  G11C2213/77 ,  G11C2213/81 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02557 ,  H01L21/0256 ,  H01L21/02603 ,  H01L21/02617 ,  H01L21/02628 ,  H01L21/02645 ,  H01L21/02653 ,  H01L23/53276 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/125 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/267 ,  H01L29/73 ,  H01L29/7781 ,  H01L29/78696 ,  H01L29/861 ,  H01L29/868 ,  H01L31/0352 ,  H01L31/08 ,  H01L33/18 ,  H01L51/0048 ,  H01L51/0595 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/3011 ,  Y02E10/549 ,  Y10S977/936 ,  Y10S977/938 ,  Y10S977/958 ,  Y10T428/2929 ,  Y10T428/298 ,  H01L2924/00

Abstract: The present invention relates generally to sub-microelectronic circuitry, and more particularly to nanometer-scale articles, including nanoscale wires which can be selectively doped at various locations and at various levels. In some cases, the articles may be single crystals. The nanoscale wires can be doped, for example, differentially along their length, or radially, and either in terms of identity of dopant, concentration of dopant, or both. This may be used to provide both n-type and p-type conductivity in a single item, or in different items in close proximity to each other, such as in a crossbar array. The fabrication and growth of such articles is described, and the arrangement of such articles to fabricate electronic, optoelectronic, or spintronic devices and components. For example, semiconductor materials can be doped to form n-type and p-type semiconductor regions for making a variety of devices such as field effect transistors, bipolar transistors, complementary inverters, tunnel diodes, light emitting diodes, sensors, and the like.

Abstract translation: 本发明一般涉及亚微电子电路，更具体地涉及纳米尺度制品，包括可以在各种位置和各种级别选择性地掺杂的纳米线。 在一些情况下，制品可以是单晶。 纳米尺寸线可以例如沿其长度或径向掺杂，或者根据掺杂剂的掺杂剂浓度，掺杂剂的浓度或两者掺杂。 这可以用于在单个项目中提供n型和p型导电性，或者在彼此非常接近的不同项目中提供，例如在横杆阵列中。 描述了这种制品的制造和生长，以及这些制品的布置以制造电子，光电子或自旋电子器件和部件。 例如，可以掺杂半导体材料以形成n型和p型半导体区域，用于制造诸如场效应晶体管，双极晶体管，互补反相器，隧道二极管，发光二极管，传感器等的各种器件。

公开(公告)号：US07192533B2

公开(公告)日：2007-03-20

申请号：US10509564

申请日：2003-03-23

Applicant: Erik Petrus Antonius Maria Bakkers ,  Freddy Roozeboom ,  Johannes Fransiscus Cornelis Maria Verhoeven ,  Paul Van Der Sluis

Inventor： Erik Petrus Antonius Maria Bakkers ,  Freddy Roozeboom ,  Johannes Fransiscus Cornelis Maria Verhoeven ,  Paul Van Der Sluis

IPC: C03C25/68

CPC classification number: B82Y10/00 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/30617 ,  H01L21/30621 ,  H01L21/3063 ,  H01L21/3065 ,  H01L21/3083 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/125

Abstract: In the method, semiconductor substrates are etched to provide nanowires, said substrates comprising a first layer of a first material and a second layer of a second material with a mutual interface, which first and second materials are different. They may be different in the doping type. Alternatively, the main constituent of the material may be different, for example SiGe or SiC versus Si, or InP versus InAs. In the resulting nanowires, the interface is atomically sharp. The electronic devices having nanowires between a first and second electrode accordingly have very good electroluminescent and optoelectronic properties.

Abstract translation: 在该方法中，蚀刻半导体衬底以提供纳米线，所述衬底包括第一材料的第一层和具有相互界面的第二材料的第二层，该第一和第二材料是不同的。 它们在掺杂类型中可能不同。 或者，材料的主要成分可以是不同的，例如SiGe或SiC相对于Si，或InP对InAs。 在所得的纳米线中，界面是原子锋利的。 因此，在第一和第二电极之间具有纳米线的电子器件具有非常好的电致发光和光电子性质。

公开(公告)号：US06972228B2

公开(公告)日：2005-12-06

申请号：US10387623

申请日：2003-03-12

Applicant: Brian S. Doyle ,  Anand S. Murthy ,  Robert S. Chau

Inventor： Brian S. Doyle ,  Anand S. Murthy ,  Robert S. Chau

IPC: H01L21/20 ,  H01L29/12 ,  H01S5/34 ,  H01L21/8242

CPC classification number: H01L29/66795 ,  B82Y10/00 ,  B82Y20/00 ,  H01L21/02381 ,  H01L21/02387 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/0262 ,  H01L29/125 ,  H01S5/341

Abstract: A method is described for forming an element of a microelectronic circuit. A sacrificial layer is formed on an upper surface of a support layer. The sacrificial layer is extremely thin and uniform. A height-defining layer is then formed on the sacrificial layer, whereafter the sacrificial layer is etched away so that a well-defined gap is left between an upper surface of the support layer and a lower surface of the height-defining layer. A monocrystalline semiconductor material is then selectively grown from a nucleation silicon site through the gap. The monocrystalline semiconductor material forms a monocrystalline layer having a thickness corresponding to the thickness of the original sacrificial layer.

Abstract translation: 描述了形成微电子电路的元件的方法。 牺牲层形成在支撑层的上表面上。 牺牲层非常薄而均匀。 然后在牺牲层上形成高度限定层，然后牺牲层被蚀刻掉，使得在支撑层的上表面和高度限定层的下表面之间留下明确限定的间隙。 然后从成核硅部位通过间隙选择性地生长单晶半导体材料。 单晶半导体材料形成具有对应于原始牺牲层的厚度的厚度的单晶层。

公开(公告)号：US20050236357A1

公开(公告)日：2005-10-27

申请号：US10509564

申请日：2003-03-23

Applicant: Erik Petrus Antonius Bakkers ,  Freddy Roozeboom ,  Johannes Fransiscus Verhoeven ,  Paul Van Der Sluis

Inventor： Erik Petrus Antonius Bakkers ,  Freddy Roozeboom ,  Johannes Fransiscus Verhoeven ,  Paul Van Der Sluis

IPC: B82B3/00 ,  H01L21/306 ,  H01L21/3063 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/06 ,  H01L29/12 ,  H01L29/786 ,  B44C1/22

CPC classification number: B82Y10/00 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/30617 ,  H01L21/30621 ,  H01L21/3063 ,  H01L21/3065 ,  H01L21/3083 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/125

Abstract: In the method, semiconductor substrates are etched to provide nanowires, said substrates comprising a first layer of a first material and a second layer of a second material with a mutual interface, which first and second materials are different. They may be different in the doping type. Alternatively, the main constituent of the material may be different, for example SiGe or SiC versus Si, or InP versus InAs. In the resulting nanowires, the interface is atomically sharp. The electronic devices having nanowires between a first and second electrode accordingly have very good electroluminescent and optoelectronic properties.

Abstract translation: 在该方法中，蚀刻半导体衬底以提供纳米线，所述衬底包括第一材料的第一层和具有相互界面的第二材料的第二层，该第一和第二材料是不同的。 它们在掺杂类型中可能不同。 或者，材料的主要成分可以是不同的，例如SiGe或SiC相对于Si，或InP对InAs。 在所得的纳米线中，界面是原子锋利的。 因此，在第一和第二电极之间具有纳米线的电子器件具有非常好的电致发光和光电子性质。