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    Semiconductor structure and forming method thereof
    75.
    发明授权
    Semiconductor structure and forming method thereof 有权

    公开(公告)号：US12080596B2

    公开(公告)日：2024-09-03

    申请号：US17223253

    申请日：2021-04-06

    申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

    发明人： Jisong Jin ,  Abraham Yoo

    IPC分类号： H01L21/768 ,  H01L21/48 ,  H01L23/522

    CPC分类号： H01L21/76877 ,  H01L21/486 ,  H01L21/76802 ,  H01L23/5226

    摘要： A semiconductor structure and a forming method thereof are provided, and the forming method includes: providing a base; forming, on the base, a plurality of conductive function layers extending in a first direction and sequentially arranged in a second direction, a bottom dielectric layer located on the base between the conductive function layers, and a blocking structure located in the conductive function layer, the blocking structure segmenting the conductive function layers located on two sides of the blocking structure in the first direction; forming a top dielectric layer covering the bottom dielectric layer, the conductive function layers, and the blocking structure; etching the top dielectric layer located above a junction of the blocking structure and the conductive function layer and a part of the blocking structure located at a side wall of the conductive function layer, to form a via running through the top dielectric layer and exposing a part of a top and a part of a side wall of the conductive function layer; and filling the via with a via interconnection structure, the via interconnection structure being in contact with the part of the top and the part of the side wall of the conductive function layer. Therefore, embodiments of the present disclosure are helpful to improve the performance of the semiconductor structure.

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    78.
    发明公开
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20240290717A1

    公开(公告)日：2024-08-29

    申请号：US18586819

    申请日：2024-02-26

    申请人： Kioxia Corporation

    发明人： Hideto TAKEKIDA

    IPC分类号： H01L23/528 ,  G11C5/06 ,  H01L23/522 ,  H10B41/27 ,  H10B43/27

    CPC分类号： H01L23/5283 ,  G11C5/063 ,  H01L23/5226 ,  H10B41/27 ,  H10B43/27

    摘要： In one embodiment, a semiconductor device includes a memory cell array, a first interconnect layer provided below the memory cell array, and including a plurality of first bit lines that extend in a first direction, and a second interconnect layer provided below the memory cell array, and including a plurality of first source lines that extend in a second direction different from the first direction, the second interconnect layer being different from the first interconnect layer. The device further includes a third interconnect layer provided above the memory cell array, and including a plurality of second source lines that extend in the second direction, and a fourth interconnect layer provided above the memory cell array, and including a plurality of second bit lines that extend in the first direction, the fourth interconnect layer being different from the third interconnect layer.

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    80.
    发明公开
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开

    公开(公告)号：US20240290715A1

    公开(公告)日：2024-08-29

    申请号：US18399335

    申请日：2023-12-28

    申请人： Socionext Inc.

    发明人： Yasuhiko MAKI

    IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L25/065

    CPC分类号： H01L23/5283 ,  H01L23/5226 ,  H01L25/0657 ,  H01L2225/06541

    摘要： In a semiconductor integrated circuit device, a first semiconductor chip includes: a buried power rail that supplies first power; and a power line that is provided in a layer above the buried power rail and supplies second power. The buried power rail receives supply of the first power from the back face of the first semiconductor chip via a first through electrode, and the power line receives supply of the second power from the back face of the first semiconductor chip via a second through electrode. The cross-sectional area of the second through electrode is greater than the cross-sectional area of the first through electrode.