公开(公告)号：US20240056057A1

公开(公告)日：2024-02-15

申请号：US18366917

申请日：2023-08-08

申请人： NXP B.V.

发明人： Pierre Pascal Savary ,  Mohamad El Ozeir ,  Stephane Damien Thuriés

IPC分类号： H03H11/24 ,  H03F3/193

CPC分类号： H03H11/245 ,  H03F3/193 ,  H03F2200/451

摘要： In accordance with a first aspect of the present disclosure, a tunable attenuator is provided, comprising: one or more transformer windings configured to facilitate attenuating a signal; one or more conductive loops provided underneath the transforming windings; a controller configured to control an amount of current flowing through the conductive loops, thereby providing a tunable attenuation of said signal. In accordance with a second aspect of the present disclosure, a corresponding method of producing a tunable attenuator is conceived.

公开(公告)号：US20240048146A1

公开(公告)日：2024-02-08

申请号：US18357689

申请日：2023-07-24

申请人： NXP B.V.

发明人： Shagun Bajoria ,  Muhammed Bolatkale ,  Lucien Johannes Breems ,  Robert Rutten ,  Mohammed Abo Alainein

IPC分类号： H03M1/06

CPC分类号： H03M1/0602

摘要： A circuit 100 is described comprising (i) a first digital-to-analog converter 110, (ii) a second digital-to-analog converter 111, (iii) a plurality of unit elements 120, and (iv) switching circuitry 130. The switching circuitry 130 is adapted so that in a first switching state 231, a set of unit elements 221 of the plurality of unit elements 120 forms part of the first digital-to-analog converter 110, and in a second switching state 232, the set of unit elements 221 forms part of the second digital-to-analog converter 111. Furthermore, a corresponding method of operating a circuit 100 is described.

公开(公告)号：US20240038683A1

公开(公告)日：2024-02-01

申请号：US17815638

申请日：2022-07-28

申请人： NXP B.V.

发明人： Tzu Ya Fang ,  Yen-Chih Lin ,  Jian Nian Chen ,  Moly Lee ,  Yi Xiu Xie ,  Vanessa Wyn Jean Tan ,  Yao Jung Chang ,  Yi-Hsuan Tsai ,  Xiu Hong Shen ,  Kuan Lin Huang

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

CPC分类号： H01L23/562 ,  H01L25/0657 ,  H01L24/20 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L21/6835 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L24/19 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2224/214 ,  H01L2924/17151 ,  H01L2924/351 ,  H01L2221/68372

摘要： A method of manufacturing a semiconductor device is provided. The method includes placing a package substrate on a carrier substrate, forming a frame on the package substrate, and affixing an active side of a semiconductor die on the package substrate. The semiconductor die together with the frame and the package substrate form a cavity between the semiconductor die and the package substrate. At least a portion of the semiconductor die and the package substrate are encapsulated with an encapsulant. The frame is configured to prevent the encapsulant from entering the cavity.

公开(公告)号：US20240030743A1

公开(公告)日：2024-01-25

申请号：US17814589

申请日：2022-07-25

申请人： NXP B.V.

发明人： Ulrich Andreas Muehlmann ,  Michael Schober

IPC分类号： H02J50/00 ,  H04B1/40 ,  G01R19/25

CPC分类号： H02J50/001 ,  H04B1/40 ,  G01R19/2503

摘要： A sensor node is provided having a radio frequency (RF) circuit and a sensor interface circuit. The RF circuit wirelessly harvests energy from an external device such as a smart phone to produce a voltage at an output to charge a storage capacitor. The sensor interface circuit is configured to communicate with a sensor. In response to a request from the external device, the sensor node provides a voltage level of the capacitive element to the external device. The external device uses the voltage level to determine capabilities of the sensor node and to control sensing functions of the sensor node. In another embodiment, a method is provided to operate the sensor node.

公开(公告)号：US20240030308A1

公开(公告)日：2024-01-25

申请号：US17813504

申请日：2022-07-19

申请人： NXP B.V.

发明人： Ljubo Radic ,  Johannes Josephus Theodorus Marinus Donkers ,  Bernhard Grote

IPC分类号： H01L29/66 ,  H01L29/737 ,  H01L29/10

CPC分类号： H01L29/66242 ,  H01L29/7378 ,  H01L29/7375 ,  H01L29/1004

摘要： A semiconductor device, such as a heterojunction bipolar transistor (HBT), may include an extrinsic base region that is connected to a collector region via semiconductor material formed in an opening in one or more dielectric layers interposed between the extrinsic base region and the collector region. The extrinsic base region may be formed from monocrystalline semiconductor material, such as silicon or silicon germanium, via selective epitaxial growth. An intrinsic base region may be formed adjacent to the extrinsic base region and may be interposed directly between the collector region and an intrinsic emitter region. A HBT with such an arrangement may have reduced base-collector capacitance and reduced base resistance compared to some conventional HBTs.

公开(公告)号：US11881425B2

公开(公告)日：2024-01-23

申请号：US18047329

申请日：2022-10-18

申请人： NXP B.V.

发明人： Antonius Hendrikus Jozef Kamphuis ,  Guido Albermann ,  Johannes Cobussen

IPC分类号： B29C65/00 ,  H01L21/683 ,  H01L21/673 ,  B29C65/56 ,  B29C65/58 ,  B29C65/50

CPC分类号： H01L21/6836 ,  H01L21/673 ,  B29C65/50 ,  B29C65/565 ,  B29C65/58 ,  H01L21/6838 ,  H01L2221/68327

摘要： A technique for handling an integrated circuit/tape assembly having a plurality of integrated circuits supported by underlying dicing tape involves placing the integrated circuit/tape assembly on a bottom file frame carrier (FFC) frame having structure (e.g., an inner rim or flexible pegs), placing a top FFC frame having a central opening over the integrated circuit/tape assembly, and mating the top and bottom FFC frames such that the dicing tape is pulled over the structure thereby laterally stretching the dicing tape, which breaks wafer saw bows holding the integrated circuits together. The lateral stretching of the dicing tape increases distance between adjacent integrated circuits in at least two mutually orthogonal lateral directions, thereby inhibiting the adjacent integrated circuits from colliding during shipment or storage for subsequent processing. The resulting assembly can be thinner than conventional FFC configurations, which results in more efficient shipment and storage.

公开(公告)号：US11879990B2

公开(公告)日：2024-01-23

申请号：US17337942

申请日：2021-06-03

申请人： NXP B.V.

发明人： Haridas Vilakathara ,  Kai Peter Ludwig Gossner ,  Artur Tadeusz Burchard

IPC分类号： G01S7/40

CPC分类号： G01S7/40 ,  G01S7/4056 ,  G01S7/4069

摘要： In one example, a continuous-wave radar circuit receives reflection signals, computer processing circuitry processes data corresponding to the reflection signals, and emulation circuitry introduces a plurality of diagnostic data sets into the radar circuit to cause the radar circuit to process simulated reflection signals as though the simulated reflection signals are reflections from objects remote from the apparatus. The radar circuit may receive the reflection signals in response to chirp sequences actually transmitted as reflections from objects.

公开(公告)号：US11876524B2

公开(公告)日：2024-01-16

申请号：US17809315

申请日：2022-06-28

申请人： NXP B.V.

发明人： Muhammed Bolatkale

IPC分类号： H03M1/10 ,  H03M1/00 ,  H03M1/06 ,  H03M3/00 ,  H03M1/12

CPC分类号： H03M1/001 ,  H03M1/0629 ,  H03M1/00 ,  H03M1/12 ,  H03M3/00

摘要： There is described a hybrid ADC device for converting an analog input signal (Vin) into a digital output signal (Vout), the device comprising a first ADC circuit configured to receive the analog input signal (Vin) and convert it into a first digital signal (Y0); a DAC circuit configured to receive the first digital signal and convert it into a first analog signal; a delay circuit configured to delay the analog input signal; a first combiner configured to generate an analog residual signal by subtracting the first analog signal from the delayed analog input signal; a second ADC circuit configured to receive the residual analog signal and convert it into a second digital signal (Y1); a filter circuit configured to receive the first digital signal and output a filtered first digital signal (Y0′), the filter circuit having a transfer function corresponding to a combined transfer function of the DAC circuit and the second ADC circuit; and a second combiner configured to generate the digital output signal (Vout) by adding the second digital signal and the filtered first digital signal, wherein the first ADC circuit comprises an anti-aliasing filter. Furthermore, a corresponding method and an automobile radar system are described.

公开(公告)号：US20230421413A1

公开(公告)日：2023-12-28

申请号：US18338754

申请日：2023-06-21

申请人： NXP B.V.

发明人： Vincent Pierre Martinez

IPC分类号： H04L25/02 ,  H04L27/26 ,  H04L25/03

CPC分类号： H04L25/0204 ,  H04L27/2647 ,  H04L25/0212 ,  H04L27/2613 ,  H04L25/03019

摘要： RF signal is received (1006). The received RF signal includes a first RF signal encoding a first orthogonal frequency-division multiplexing (OFDM) symbol of a first long-term evolution (LTE) V2X data packet. A channel estimation in the time domain is determined (1012) using the received signal and an as-transmitted time domain version of an L-LTF symbol is determined (1014). The channel estimation in the time domain is applied to the as-transmitted time domain version of the L-LTF symbol to determine an as-transmitted version of the L-LTF symbol that exhibits channel fading (1018). A first portion of the as-transmitted version of the L-LTF symbol that exhibits channel fading is subtracted from a second portion of the received RF signal (1022) to remove inter-symbol interference from the received signal to generate a second received RF signal.

公开(公告)号：US20230421314A1

公开(公告)日：2023-12-28

申请号：US18338795

申请日：2023-06-21

申请人： NXP B.V.

发明人： Vincent Pierre Martinez

IPC分类号： H04L5/00 ,  H04L25/02 ,  H04L25/03

CPC分类号： H04L5/0007 ,  H04L5/0028 ,  H04L25/0202 ,  H04L25/03006 ,  H04L2025/0377

摘要： The received RF signal includes a first RF signal encoding a first orthogonal frequency-division multiplexing (OFDM) symbol of a first long-term evolution (LTE) V2X data packet. A legacy long training field (L-LTF) symbol is determined using the received RF signal (608), a channel estimation is calculated (612) using the L-LTF symbol, and legacy signal (L-SIG) field control bits are determined (614) from the received RF signal, the L-SIG field control bits including a plurality of IQ samples. A plurality of candidate L-SIG decodings are generated (618) using the IQ samples and the channel estimation, wherein each candidate L-SIG decoding of the plurality of L-SIG decodings is generated by setting a different number of IQ samples in the L-SIG field control bits to zero values (616), and a first L-SIG decoding of the plurality of candidate L-SIG decodings is identified (624). A data field from the received RF signal is decoded using the first L-SIG decoding (626).