公开(公告)号：US11450364B2

公开(公告)日：2022-09-20

申请号：US17337889

申请日：2021-06-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yi-Chun Shih ,  Chia-Fu Lee ,  Yu-Der Chih ,  Jonathan Tsung-Yung Chang

IPC: G11C7/12 ,  G11C7/10 ,  G11C5/06 ,  G11C16/04 ,  G11C16/30

Abstract: Systems and methods are provided for a computing-in memory circuit that includes a bit line and a plurality of computing cells connected to the bit line. Each of the plurality of computing cells includes a memory element, having a data output terminal; a logic element, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the data output terminal of the memory element, the second input terminal receives a select signal; and a capacitor, having a first terminal and a second terminal, where the first terminal is coupled to the output terminal of the logic element, the second terminal is coupled to the bit line. A voltage of the bit line is driven by the plurality of computing cells.

公开(公告)号：US20220293141A1

公开(公告)日：2022-09-15

申请号：US17829333

申请日：2022-05-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ku-Feng Lin ,  Yu-Der Chih

IPC: G11C7/06 ,  G11C7/08 ,  G11C7/12

Abstract: A sense amplifier includes a voltage comparator with offset compensation, a first clamping device and a second clamping device. The voltage comparator is coupled to a bit line and a reference bit line respectively, and configured to compare a first input voltage and a second input voltage to output a sensing signal. The first clamping circuit and the second clamping circuit trim a voltage corresponding to the bit line and a voltage corresponding to the reference bit line respectively to match the voltage corresponding to the reference bit line with the voltage corresponding to the bit line.

公开(公告)号：US20220215880A1

公开(公告)日：2022-07-07

申请号：US17140605

申请日：2021-01-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hiroki Noguchi ,  Yu-Der Chih ,  Yih Wang

IPC: G11C13/00 ,  G11C11/16 ,  G11C11/22

Abstract: A memory device includes: a memory cell array comprising a plurality of memory cells; a temperature sensor configured to detect a temperature of the memory cell array; a write circuit configured to write data into the plurality of memory cells; and a controller coupled to the temperature sensor and the write circuit, wherein the controller is configured to determine a target write pulse width used by the write circuit based on the detected temperature of the memory device.

公开(公告)号：US11373706B2

公开(公告)日：2022-06-28

申请号：US17105483

申请日：2020-11-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Der Chih

IPC: G11C11/00 ,  G11C13/00

Abstract: The disclosure is directed to a memory circuit, an electronic device, and a method for implementing a ternary weight for in-memory computing. According to an aspect of the disclosure, the memory circuit includes a first memory cell having a first resistor; a second memory cell having a second resistor, a write driver configured to set the first resistor to a first resistance value, a second write driver configured to set the second resistor to a second resistance value, a differential current sensing circuit configured to determine a differential current between the first memory cell and the second memory cell based on the first resistance value and the second resistance value, and a ternary weight detector configured to determine a ternary weight which is selected among a first ternary weight, a second ternary weight, and a third ternary weight based on the differential current.

公开(公告)号：US20220157351A1

公开(公告)日：2022-05-19

申请号：US17096966

申请日：2020-11-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ku-Feng Lin ,  Yu-Der Chih

IPC: G11C7/06 ,  G11C7/12 ,  G11C7/08

Abstract: A sense amplifier includes a voltage comparator with offset compensation, a first clamping device and a second clamping device. The voltage comparator is coupled to a bit line and a reference bit line respectively, and configured to compare a first input voltage and a second input voltage to output a sensing signal. The first clamping circuit and the second clamping circuit trim a voltage corresponding to the bit line and a voltage corresponding to the reference bit line respectively to match the voltage corresponding to the reference bit line with the voltage corresponding to the bit line.

公开(公告)号：US11204826B2

公开(公告)日：2021-12-21

申请号：US16535787

申请日：2019-08-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hiroki Noguchi ,  Yu-Der Chih ,  Hsueh-Chih Yang ,  Randy Osborne ,  Win San Khwa

IPC: G06F11/10 ,  G11C29/52 ,  G11C11/16

Abstract: A memory device, such as a MRAM device, includes a plurality of memory macros, where each includes an array of memory cells and a first ECC circuit configured to detect data errors in the respective memory macro. A second ECC circuit that is remote from the plurality of memory macros is communicatively coupled to each of the plurality of memory macros. The second ECC circuit is configured to receive the detected data errors from the first ECC circuits of the plurality of memory macros and correct the data errors.

公开(公告)号：US20210241830A1

公开(公告)日：2021-08-05

申请号：US17106725

申请日：2020-11-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Zheng-Jun Lin ,  Chung-Cheng Chou ,  Yu-Der Chih ,  Pei-Ling Tseng

IPC: G11C13/00

Abstract: The disclosed invention presents a self-tracking reference circuit that compensates for IR drops and achieves the target resistance state at different temperatures after write operations. The disclosed self-tracking reference circuit includes a replica access path, a configurable resistor network, a replica selector mini-array and a step current generator that track PVT variations to provide a PVT tracking level for RRAM verify operation.

公开(公告)号：US10372948B2

公开(公告)日：2019-08-06

申请号：US14969621

申请日：2015-12-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Kai-Chun Lin ,  Ku-Feng Lin ,  Hung-Chang Yu ,  Yu-Der Chih

IPC: G06F21/79 ,  G06F12/14

Abstract: A memory device is provided which comprises a memory array, a first scrambling circuit and a second scrambling circuit. The first scrambling circuit is configured to provide first scrambled data with a first scrambling pattern in response to input data. The second scrambling circuit is configured to provide second scrambled data with a second scrambling pattern in response to the first scrambled data.

公开(公告)号：US10056921B2

公开(公告)日：2018-08-21

申请号：US15247130

申请日：2016-08-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Shih-Lien Linus Lu ,  Yu-Der Chih

IPC: H03M13/35 ,  G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  H03M13/05 ,  H03M13/29 ,  H03M13/00

CPC classification number: H03M13/356 ,  G06F11/1012 ,  G11C29/52 ,  H03M13/05 ,  H03M13/13 ,  H03M13/19 ,  H03M13/29 ,  H03M13/353 ,  H03M13/6508 ,  H03M13/6516

Abstract: A memory system is disclosed. The memory system includes: a memory; a first ECC circuit used to encode information bits of a first length into a codeword of a first ECC scheme, and to decode a codeword of the first ECC scheme read from the memory into decoded information bits of the first length; a second ECC circuit used to encode information bits of a second length into a codeword of a second ECC scheme, and to decode a codeword of the second ECC scheme read from the memory into decoded information bits of the second length; and a control circuit used to combine a plurality sets of the decoded information bits of the first length into the information bits of the second length, and to separate the decoded information bits of the second length into a plurality sets of the information bits of the first length.

公开(公告)号：US12230323B2

公开(公告)日：2025-02-18

申请号：US18304297

申请日：2023-04-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chin-I Su ,  Chung-Cheng Chou ,  Yu-Der Chih ,  Zheng-Jun Lin

IPC: G11C13/00

Abstract: A memory circuit includes a first driver circuit, a memory cell array including a first column of memory cells, a first transistor coupled between the first driver circuit and the memory cell array, a second driver circuit, a first column of tracking cells and a header circuit coupled to the first driver circuit and the second driver circuit. The first transistor is configured to receive a first select signal. The first column of tracking cells is configured to track a leakage current of the first column of memory cells, and is coupled between a first conductive line and a second conductive line, the first conductive line being coupled to the second driver circuit.