公开(公告)号：US20140273363A1

公开(公告)日：2014-09-18

申请号：US13804679

申请日：2013-03-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Chao Chiu ,  Nian-Fuh Cheng ,  Chen-Yu Chen ,  Ming-Feng Shieh ,  Chih-Ming Lai ,  Wen-Chun Huang ,  Ru-Gun Lin

IPC: H01L21/308 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure provides a method of semiconductor device fabrication including forming a mandrel on a semiconductor substrate is provided. The method continues to include oxidizing a region the mandrel to form an oxidized region, wherein the oxidized region abuts a sidewall of the mandrel. The mandrel is then removed from the semiconductor substrate. After removing the mandrel, the oxidized region is used to pattern an underlying layer formed on the semiconductor substrate.

Abstract translation: 本公开提供了一种半导体器件制造方法，包括在半导体衬底上形成心轴。 该方法继续包括使心轴氧化形成氧化区域，其中氧化区域邻接心轴的侧壁。 然后从半导体衬底去除心轴。 在去除心轴之后，使用氧化区域对形成在半导体衬底上的下层进行图案化。

公开(公告)号：US20140264717A1

公开(公告)日：2014-09-18

申请号：US13871644

申请日：2013-04-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ming-Feng Shieh ,  Chen-Yu Chen

IPC: H01L29/06 ,  H01L21/308 ,  H01L21/76

CPC classification number: H01L27/0886 ,  H01L21/28123 ,  H01L21/3086 ,  H01L21/76 ,  H01L21/823431 ,  H01L29/06 ,  H01L29/0649 ,  H01L29/6681

Abstract: A method of forming a fin structure of a semiconductor device includes providing a substrate, creating a mandrel pattern over the substrate, depositing a first spacer layer over the mandrel pattern, and removing portions of the first spacer layer to form first spacer fins. The method also includes performing a first fin cut process to remove a subset of the first spacer fins, depositing a second spacer layer over the un-removed first spacer fins, and removing portions of the second spacer layer to form second spacer fins. The method further includes forming fin structures, and performing a second fin cut process to remove a subset of the fin structures.

Abstract translation: 一种形成半导体器件的翅片结构的方法包括提供衬底，在衬底上形成心轴图案，在心轴图案上沉积第一间隔层，以及去除第一间隔层的部分以形成第一间隔片。 该方法还包括执行第一翅片切割过程以去除第一间隔物翅片的子集，在未去除的第一间隔物翅片上沉积第二间隔层，以及去除第二间隔层的部分以形成第二间隔片。 该方法还包括形成翅片结构，以及执行第二翅片切割过程以去除翅片结构的子集。

公开(公告)号：US08806397B2

公开(公告)日：2014-08-12

申请号：US14018133

申请日：2013-09-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Hsun Wang ,  Chih-Sheng Chang ,  Yi-Tang Lin ,  Ming-Feng Shieh

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G03F1/00 ,  G06F17/5068 ,  H01L29/66795

Abstract: A method of generating a layout for a device includes receiving a first layout including a plurality of active regions, each active region of the plurality of active regions having sides. The method further includes defining a plurality of elongate mandrels that each extend in a first direction and are spaced apart from one another in a second direction perpendicular to the first direction. The method further includes for each adjacent pair of partially-parallel active regions of the plurality of active regions having a minimum distance less than a specified minimum spacing, connecting at least a portion of nearest ends of pairs of elongate mandrels, each mandrel of a pair from a different active region. The method further includes generating a second layout including a plurality of elongate mandrels in the plurality of active regions, and connective elements between active regions of at least one adjacent pair of active regions.

Abstract translation: 产生装置的布局的方法包括接收包括多个有效区域的第一布局，所述多个有源区域中的每个有源区域具有边。 该方法还包括限定多个细长心轴，每个细长心轴在第一方向上延伸并且在垂直于第一方向的第二方向上彼此间隔开。 该方法还包括对于多个有源区域中的每个相邻的一对部分平行的有源区域具有小于规定的最小间隔的最小距离，连接成对细长心轴的最近端的至少一部分，一对的每个心轴 来自不同的活跃区域。 该方法还包括产生包括多个有源区域中的多个细长心轴的第二布局，以及至少一个相邻的一对有源区域的有源区域之间的连接元件。

公开(公告)号：US20240379551A1

公开(公告)日：2024-11-14

申请号：US18779523

申请日：2024-07-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hung-Chung Chien ,  Chao-Hong Chen ,  Ming-Feng Shieh

IPC: H01L23/528 ,  H01L21/02 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor structure includes channel structures vertically stacked, a gate structure engaging the channel structures, an epitaxial feature abutting the channel structures, a backside interconnect layer disposed under the epitaxial feature, and a backside metal contact disposed directly under the epitaxial feature and electrically coupling the epitaxial feature to the backside interconnect layer. In a cross-sectional view of the semiconductor structure along a lengthwise direction of the channel structures, the backside metal contact extends to a position directly under the channel structures.

公开(公告)号：US11876054B2

公开(公告)日：2024-01-16

申请号：US17323396

申请日：2021-05-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chen-Yu Chen ,  Ming-Feng Shieh ,  Ching-Yu Chang

IPC: H01L23/544 ,  G03F7/00 ,  H01L21/302 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L23/544 ,  G03F7/70633 ,  G03F7/70683 ,  H01L21/302 ,  H01L29/0649 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An overlay mark includes a first feature extending in an X-direction, wherein the first feature is a first distance from a substrate. The overlay mark further includes a second feature extending in a Y-direction perpendicular to the X-direction, wherein the second feature is a second distance from the substrate, and the second distance is different from the first distance, wherein at least one of the first feature or the second feature comprises a conductive material. The overlay mark further includes a third feature extending in the X-direction and the Y-direction, wherein the third feature is a third distance from the substrate, and the third distance is different from the first distance and the second distance. The first distance, the second distance and the third distance from the substrate are along a Z-direction perpendicular to both the X-direction and the Y-direction.

公开(公告)号：US20220102274A1

公开(公告)日：2022-03-31

申请号：US17344478

申请日：2021-06-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hung-Chung Chien ,  Chao-Hong Chen ,  Ming-Feng Shieh

IPC: H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/40 ,  H01L29/66

Abstract: A method of manufacturing a semiconductor device includes forming a fin structure over a substrate, forming a sacrificial gate structure over the fin structure, and etching a source/drain (S/D) region of the fin structure to form an S/D recess. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method further includes depositing an insulating dielectric layer in the S/D recess, depositing an etch protection layer over a bottom portion of the insulating dielectric layer, and partially removing the insulating dielectric layer. The method further includes growing an epitaxial S/D feature in the S/D recess. The bottom portion of the insulating dielectric layer interposes the epitaxial S/D feature and the substrate.

公开(公告)号：US11239365B2

公开(公告)日：2022-02-01

申请号：US16726405

申请日：2019-12-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shao-Ming Yu ,  Chang-Yun Chang ,  Chih-Hao Chang ,  Hsin-Chih Chen ,  Kai-Tai Chang ,  Ming-Feng Shieh ,  Kuei-Liang Lu ,  Yi-Tang Lin

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/67 ,  H01L27/088

Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.

公开(公告)号：US10770303B2

公开(公告)日：2020-09-08

申请号：US16397439

申请日：2019-04-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Ming Chang ,  Ming-Feng Shieh ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Tsai-Sheng Gau

IPC: H01L21/308 ,  G03F7/20 ,  G03F1/00 ,  H01L29/66 ,  H01L27/12 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/302 ,  H01L21/033 ,  H01L21/02

Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. The method includes providing a substrate and a patterning-target layer over the substrate; patterning the patterning-target layer to form a main pattern; forming a middle layer over the patterning-target layer and a hard mask layer over the middle layer; patterning the hard mask layer to form a first cut pattern; patterning the hard mask layer to form a second cut pattern, a combined cut pattern being formed in the hard mask layer as a union of the first cut pattern and the second cut pattern; transferring the combined cut pattern to the middle layer; etching the patterning-target layer using the middle layer as an etching mask to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting an intersection portion between main pattern and the combined cut pattern.

公开(公告)号：US10032664B2

公开(公告)日：2018-07-24

申请号：US15174699

申请日：2016-06-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Ming Chang ,  Ken-Hsien Hsieh ,  Chih-Ming Lai ,  Ming-Feng Shieh ,  Ru-Gun Liu ,  Tsai-Sheng Gau

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L23/528 ,  H01L21/3213 ,  H01L23/522

Abstract: The present disclosure describes methods for transferring a desired layout into a target layer on a semiconductor substrate. An embodiment of the methods includes forming a first desired layout feature as a first line over the target layer; forming a spacer around the first line; depositing a spacer-surrounding material layer; removing the spacer to form a fosse pattern trench surrounding the first line; and transferring the fosse pattern trench into the target layer to form a fosse feature trench in the target layer, wherein the fosse feature trench surrounds a first portion of the target layer that is underneath a protection layer. In some embodiments, the method further includes patterning a second desired layout feature of the desired layout into the target layer wherein the fosse feature trench and the protection layer serve to self-align the second desired layout feature with the first portion of the target layer.

公开(公告)号：US09929153B2

公开(公告)日：2018-03-27

申请号：US14057183

申请日：2013-10-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Feng Shieh ,  Weng-Hung Tseng ,  Tzung-Hua Lin ,  Hung-Chang Hsieh

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/84

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/845

Abstract: A method of fabricating a fin-like field-effect transistor (FinFET) device is disclosed. The method includes forming a mandrel features over a substrate, the mandrel feature and performing a coarse cut to remove one or more mandrel features to form a coarse space. After the coarse cut, the substrate is etched by using the mandrel features, with the coarse space as an etch mask, to form fins. A spacer layer is deposited to fully fill in a space between adjacent fins and cover sidewalls of the fins adjacent to the coarse space. The spacer layer is etched to form sidewall spacers on the fins adjacent to the coarse space. A fine cut is performed to remove a portion of one or more mandrel features to form an end-to-end space. An isolation trench is formed in the end-to-end space and the coarse space.