公开(公告)号：US10886182B2

公开(公告)日：2021-01-05

申请号：US16427802

申请日：2019-05-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chao-Ching Cheng ,  I-Sheng Chen ,  Hung-Li Chiang ,  Tzu-Chiang Chen

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/311 ,  H01L29/66

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers containing Ge and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A Ge concentration in the first semiconductor layers is increased. A sacrificial gate structure is formed over the fin structure. A source/drain epitaxial layer is formed over a source/drain region of the fin structure. The sacrificial gate structure is removed. The second semiconductor layers in a channel region are removed, thereby releasing the first semiconductor layers in which the Ge concentration is increased. A gate structure is formed around the first semiconductor layers in which the Ge concentration is increased.

公开(公告)号：US10804367B2

公开(公告)日：2020-10-13

申请号：US15719686

申请日：2017-09-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Cheng ,  Wei-Sheng Yun ,  I-Sheng Chen ,  Shao-Ming Yu ,  Tzu-Chiang Chen ,  Chih Chieh Yeh

IPC: H01L29/165 ,  H01L21/8236 ,  H01L27/092 ,  H01L29/51 ,  H01L29/66 ,  H01L29/10 ,  H01L27/06 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/775 ,  H01L29/40

Abstract: A semiconductor device includes a substrate; an I/O device over the substrate; and a core device over the substrate. The I/O device includes a first gate structure having an interfacial layer; a first high-k dielectric stack over the interfacial layer; and a conductive layer over and in physical contact with the first high-k dielectric stack. The core device includes a second gate structure having the interfacial layer; a second high-k dielectric stack over the interfacial layer; and the conductive layer over and in physical contact with the second high-k dielectric stack. The first high-k dielectric stack includes the second high-k dielectric stack and a third dielectric layer.

公开(公告)号：US10546938B2

公开(公告)日：2020-01-28

申请号：US16228872

申请日：2018-12-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yee-Chia Yeo ,  Sung-Li Wang ,  Chi On Chui ,  Jyh-Cherng Sheu ,  Hung-Li Chiang ,  I-Sheng Chen

IPC: H01L29/45 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L23/522 ,  H01L27/088 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78

Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.

公开(公告)号：US20190393357A1

公开(公告)日：2019-12-26

申请号：US16235987

申请日：2018-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Sheng Chen ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Carlos H. Diaz

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06

Abstract: A nanowire FET device includes a vertical stack of nanowire strips configured as the semiconductor body. One or more of the top nanowire strips are receded and are shorter than the rest of the nanowire strips stacked lower. Inner spacers are uniformly formed adjacent to the receded nanowire strips and the rest of the nanowire strips. Source/drain structures are formed outside the inner spacers and a gate structure is formed inside the inner spacers, which wraps around the nanowire strips.

公开(公告)号：US10431696B2

公开(公告)日：2019-10-01

申请号：US15873929

申请日：2018-01-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wilman Tsai ,  Cheng-Hsien Wu ,  I-Sheng Chen ,  Stefan Rusu

IPC: H01L29/78 ,  H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/49

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate including a first fin portion and a first nanowire over the first fin portion. The first nanowire has a polygonal cross-section. The semiconductor device structure also includes a first gate structure surrounding the first nanowire, and two first source/drain portions adjacent to the first nanowire.

公开(公告)号：US10403550B2

公开(公告)日：2019-09-03

申请号：US15885359

申请日：2018-01-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Li Chiang ,  Chao-Ching Cheng ,  Chih-Liang Chen ,  Tzu-Chiang Chen ,  Ta-Pen Guo ,  Yu-Lin Yang ,  I-Sheng Chen ,  Szu-Wei Huang

IPC: H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer.

公开(公告)号：US10170374B2

公开(公告)日：2019-01-01

申请号：US15632449

申请日：2017-06-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： I-Sheng Chen ,  Tzu-Chiang Chen ,  Cheng-Hsien Wu ,  Chih-Chieh Yeh ,  Chih-Sheng Chang

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02

Abstract: A semiconductor device includes at least one n-channel, at least one p-channel, at least one first high-k dielectric sheath, at least one second high-k dielectric sheath, a first metal gate electrode and a second metal gate electrode. The first high-k dielectric sheath surrounds the n-channel. The second high-k dielectric sheath surrounds the p-channel. The first high-k dielectric sheath and the second high-k dielectric sheath comprise different high-k dielectric materials. The first metal gate electrode surrounds the first high-k dielectric sheath. The second metal gate electrode surrounds the second high-k dielectric sheath.

公开(公告)号：US20180350591A1

公开(公告)日：2018-12-06

申请号：US16045618

申请日：2018-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Wu ,  I-Sheng Chen

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/267 ,  H01L29/20 ,  H01L29/165 ,  H01L29/04 ,  H01L29/06

Abstract: A method includes receiving a semiconductor substrate including a first semiconductor material; etching a portion of the semiconductor substrate, thereby forming a recess, a bottom portion of the recess having a first sidewall and a second sidewall intersecting with each other, one of the first and second sidewalls exposing a (111) crystallographic plane of the semiconductor substrate; and epitaxially growing a second semiconductor material in the recess, the second semiconductor material having lattice mismatch to the first semiconductor material, dislocations in the second semiconductor material due to the lattice mismatch propagating from the first sidewall to the second sidewall in a direction parallel to a top surface of the semiconductor substrate.

公开(公告)号：US20180301558A1

公开(公告)日：2018-10-18

申请号：US15487559

申请日：2017-04-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Li Chiang ,  I-Sheng Chen ,  Chi-On Chui

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L29/7851 ,  H01L21/762 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795

Abstract: A semiconductor device includes a substrate; at least one source/drain feature at least partially disposed in the substrate; an isolation structure disposed on the substrate and includes a first portion; a gate structure disposed on the first portion of the isolation structure and adjacent to the source/drain feature; and at least one gate spacer disposed on a sidewall of the gate structure, in which a top surface of the first portion of the isolation structure is in contact with the gate structure and is higher than a bottommost surface of the gate spacer.