公开(公告)号：US11948914B2

公开(公告)日：2024-04-02

申请号：US17813648

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Feng-Cheng Hsu ,  Shin-Puu Jeng ,  Shuo-Mao Chen

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L24/13 ,  H01L24/81 ,  H01L25/50 ,  H01L2924/14

Abstract: A package structure and a method of forming the same are provided. The package structure includes a package substrate, a semiconductor chip disposed over the package substrate, and an integrated device located below and bonded to the lower surface of the semiconductor chip. The semiconductor chip has a lower surface facing the package substrate and is electrically connected to the package substrate through conductive structures. The integrated device is laterally surrounded by the conductive structures, and the integrated device and the conductive structures are located within boundaries of the semiconductor chip when viewed in a direction perpendicular to the lower surface of the semiconductor chip.

公开(公告)号：US11942408B2

公开(公告)日：2024-03-26

申请号：US17749218

申请日：2022-05-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Shuo-Mao Chen ,  Feng-Cheng Hsu ,  Shin-Puu Jeng

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L25/18 ,  H01L23/14 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/49827 ,  H01L21/4803 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/49811 ,  H01L23/49894 ,  H01L25/18 ,  H01L21/4857 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5385 ,  H01L23/5389 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/73204

Abstract: A method includes: bonding a plurality of interposer dies to a first redistribution layer (RDL), each of the interposer dies comprising a substrate and a second RDL below the substrate; encapsulating the first RDL and the interposer dies; reducing a thickness of the substrate of each of the interposer dies; and electrically coupling the interposer dies to a first semiconductor die.

公开(公告)号：US11935837B2

公开(公告)日：2024-03-19

申请号：US17708666

申请日：2022-03-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Feng Wei Kuo ,  Chewn-Pu Jou ,  Shuo-Mao Chen

IPC: H01L23/538 ,  G02B6/42 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/16 ,  H01L25/18

CPC classification number: H01L23/5386 ,  G02B6/4202 ,  G02B6/4251 ,  G02B6/428 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/24 ,  H01L24/73 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/16146 ,  H01L2224/24137 ,  H01L2224/73259 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: An integrated circuit package integrates a photonic die (oDie) and an electronic die (eDie). More specifically, the integrated circuit package may include a plurality of redistribution layers communicatively coupled to at least one of the oDie and/or the eDie, where molded material at least partially surrounds the at least one of the oDie and/or the eDie.

公开(公告)号：US20230395481A1

公开(公告)日：2023-12-07

申请号：US17832374

申请日：2022-06-03

Applicant: Taiwan Semiconductor Manufacturing Company Ltd.

Inventor： Monsen Liu ,  Shang-Lun Tsai ,  Shuo-Mao Chen ,  Shin-Puu Jeng

IPC: H01L23/498 ,  H01L25/065 ,  H01L25/16 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L25/0655 ,  H01L25/162 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L21/4857 ,  H01L21/486 ,  H01L2924/1436 ,  H01L2924/1431 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73104

Abstract: A device includes a semiconductor chip and a redistribution layer (RDL) structure connected to the semiconductor chip. The redistribution layer structure comprises a first region including: a first bump connected to the semiconductor chip; a second bump; and a plurality of first redistribution layers connected between the first bump and the second bump. The RDL structure includes a second region laterally surrounding the first region, the second region including a plurality of second redistribution layers. The RDL structure includes an isolation region laterally separating the plurality of first redistribution layers from the plurality of second redistribution layer. The isolation region includes at least one region that is straight, continuous, extends from an upper surface of the redistribution layer structure to a lower surface of the first redistribution layer structure, and has at least a selected width.

公开(公告)号：US11756928B2

公开(公告)日：2023-09-12

申请号：US17726545

申请日：2022-04-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shuo-Mao Chen ,  Feng-Cheng Hsu ,  Han-Hsiang Huang ,  Hsien-Wen Liu ,  Shin-Puu Jeng ,  Hsiao-Wen Lee

IPC: H01L25/065 ,  H01L25/16 ,  H01L23/538 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31

CPC classification number: H01L25/0652 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/5383 ,  H01L25/16 ,  H01L25/50 ,  H01L23/3128 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2225/06517 ,  H01L2225/06548

Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.

公开(公告)号：US11605600B2

公开(公告)日：2023-03-14

申请号：US17071030

申请日：2020-10-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shin-Puu Jeng ,  Po-Yao Lin ,  Shuo-Mao Chen ,  Chia-Hsiang Lin

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L23/64 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

Abstract: A package structure and a formation method of a package structure are provided. The method includes forming multiple conductive vias in a carrier substrate and forming a redistribution structure over the carrier substrate. The redistribution structure has multiple polymer-containing layers and multiple conductive features. The method also includes disposing multiple chip structures over the redistribution structure. The method further includes bonding the carrier substrate to a package structure.

公开(公告)号：US11342306B2

公开(公告)日：2022-05-24

申请号：US17006863

申请日：2020-08-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shuo-Mao Chen ,  Feng-Cheng Hsu ,  Han-Hsiang Huang ,  Hsien-Wen Liu ,  Shin-Puu Jeng ,  Hsiao-Wen Lee

IPC: H01L25/065 ,  H01L25/16 ,  H01L23/538 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31

Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.

公开(公告)号：US10770437B2

公开(公告)日：2020-09-08

申请号：US16100002

申请日：2018-08-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Jui-Pin Hung ,  Feng-Cheng Hsu ,  Shuo-Mao Chen ,  Shin-Puu Jeng

IPC: H01L23/02 ,  H01L25/10 ,  H01L25/065 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H01L23/498

Abstract: The present disclosure provides a semiconductor package, including a first layer, a second layer, and a conductive array. The first layer includes a packaged die having a carrier surface and a molding surface, and a first die structure in proximity to the carrier surface. An active region of the first die structure is electrically coupled to the packaged die through a solder. The second layer includes a second die structure, the second die structure being connected to the active region of the first die structure by a first redistributed layer (RDL). The conductive array is connected to an active region of the second die structure by a second RDL. The present disclosure also provides a method for manufacturing the aforesaid semiconductor package.

公开(公告)号：US10535632B2

公开(公告)日：2020-01-14

申请号：US15388434

申请日：2016-12-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Shin-Puu Jeng ,  Feng-Cheng Hsu ,  Shuo-Mao Chen

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor package structure includes a redistribution (RDL) layer, a first chip, at least one second chip, an encapsulant and a third chip. The redistribution layer has a first surface and a second surface opposite to each other. The first chip is over the first surface of the redistribution layer and electrically connected to the redistribution layer. The second chip is over the first surface of the redistribution layer. The second chip includes a plurality of through via structures. The encapsulant is over the first surface of the distribution layer, wherein the encapsulant surrounds the first chip and the second chip. The third chip is over the encapsulant and electrically connected to the first chip through the through via structures of the second chip and the redistribution layer.

公开(公告)号：US10163860B2

公开(公告)日：2018-12-25

申请号：US15223356

申请日：2016-07-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Feng-Cheng Hsu ,  Shuo-Mao Chen ,  Jui-Pin Hung ,  Shin-Puu Jeng

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/538 ,  H01L25/00 ,  H01L21/683 ,  H01L25/18 ,  H01L23/00 ,  H01L25/03 ,  H01L25/10 ,  H05K1/02 ,  H01L23/31

Abstract: A semiconductor package structure includes an encapsulant, a first chip, a second chip, a first redistribution layer and a second redistribution layer. The encapsulant has a first surface and a second surface opposite to each other. The first chip is in the encapsulant, wherein the first chip includes a plurality of contact pads exposed from the first surface of the encapsulant. The second chip is in the encapsulant, wherein second chip includes a plurality of contact pads exposed from the second surface of the encapsulant. The first redistribution layer is over the first surface of the encapsulant and electrically connected to the contact pads of the first chip. The second redistribution layer is over the second surface of the encapsulant and electrically connected to the contact pads of the second chip.