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    Addition of carboxyl groups plasma during etching for interconnect reliability enhancement
    71.
    发明授权
    Addition of carboxyl groups plasma during etching for interconnect reliability enhancement 有权
    在蚀刻期间添加羧基等离子体以实现互连可靠性提高

    公开(公告)号：US08901007B2

    公开(公告)日：2014-12-02

    申请号：US13733222

    申请日：2013-01-03

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Cheng-Hsiung Tsai ,  Chung-Ju Lee ,  Sunil Kumar Singh ,  Tien-I Bao

    IPC: H01L21/3065 ,  H01L21/311

    CPC classification number: H01L21/3065 ,  H01L21/311 ,  H01L21/31116 ,  H01L21/76811 ,  H01L21/76813

    Abstract: The present disclosure is directed to a method of manufacturing a semiconductor structure in which a low-k dielectric layer is formed over a semiconductor substrate. Features can be formed proximate to the low-k dielectric layer by plasma etching with a plasma formed of a mixture of a CO2, CO, or carboxyl-containing source gas and a fluorine-containing source gas. The method allows for formation of damascene structures without encountering the problems associated with damage to a low-K dielectric layer.

    Abstract translation: 本公开涉及一种制造半导体结构的方法，其中在半导体衬底上形成低k电介质层。 通过用由CO 2，CO或含羧基的源气体和含氟源气体的混合物形成的等离子体蚀刻等离子体蚀刻，可以在低k电介质层附近形成特征。 该方法允许形成镶嵌结构，而不会遇到与低K电介质层的损坏相关的问题。

    ADDITION OF CARBOXYL GROUPS PLASMA DURING ETCHING FOR INTERCONNECT RELIABILITY ENHANCEMENT
    72.
    发明申请
    ADDITION OF CARBOXYL GROUPS PLASMA DURING ETCHING FOR INTERCONNECT RELIABILITY ENHANCEMENT 有权
    在互连可靠性增强的蚀刻期间加入碳氧烷等离子体

    公开(公告)号：US20140187044A1

    公开(公告)日：2014-07-03

    申请号：US13733222

    申请日：2013-01-03

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Cheng-Hsiung Tsai ,  Chung-Ju Lee ,  Sunil Kumar Singh ,  Tien-I Bao

    IPC: H01L21/3065 ,  H01L21/311

    CPC classification number: H01L21/3065 ,  H01L21/311 ,  H01L21/31116 ,  H01L21/76811 ,  H01L21/76813

    Abstract: The present disclosure is directed to a method of manufacturing a semiconductor structure in which a low-k dielectric layer is formed over a semiconductor substrate. Features can be formed proximate to the low-k dielectric layer by plasma etching with a plasma formed of a mixture of a CO2, CO, or carboxyl-containing source gas and a fluorine-containing source gas. The method allows for formation of damascene structures without encountering the problems associated with damage to a low-K dielectric layer.

    Abstract translation: 本公开涉及一种制造半导体结构的方法，其中在半导体衬底上形成低k电介质层。 通过用由CO 2，CO或含羧基的源气体和含氟源气体的混合物形成的等离子体蚀刻等离子体蚀刻，可以在低k电介质层附近形成特征。 该方法允许形成镶嵌结构，而不会遇到与低K电介质层的损坏相关的问题。

    Self-aligned interconnect structure
    76.
    发明授权
    Self-aligned interconnect structure 有权

    公开(公告)号：US11488926B2

    公开(公告)日：2022-11-01

    申请号：US16898670

    申请日：2020-06-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsin-Chieh Yao ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsi-Wen Tien ,  Yu-Teng Dai ,  Wei-Hao Liao

    IPC: H01L23/00 ,  H01L21/768

    Abstract: The present disclosure relates to a semiconductor structure including an interconnect structure disposed over a semiconductor substrate. A lower metal line is disposed at a first height over the semiconductor substrate and extends through a first interlayer dielectric layer. A second interlayer dielectric layer is disposed at a second height over the semiconductor substrate and comprises a first dielectric material. An upper metal line is disposed at a third height over the semiconductor substrate. A via is disposed at the second height. The via extends between the lower metal line and the upper metal line. A protective dielectric structure is disposed at the second height. The protective dielectric structure comprises a protective dielectric material and is disposed along a first set of opposing sidewalls of the via, the protective dielectric material differing from the first dielectric material.

    Methods of etching metals in semiconductor devices
    79.
    发明授权
    Methods of etching metals in semiconductor devices 有权

    公开(公告)号：US11158518B2

    公开(公告)日：2021-10-26

    申请号：US16582412

    申请日：2019-09-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wei-Hao Liao ,  Hsi-Wen Tien ,  Chih Wei Lu ,  Pin-Ren Dai ,  Chung-Ju Lee

    IPC: H01L23/48 ,  H01L21/3213 ,  H01L23/522 ,  H01L23/532 ,  H01L21/033 ,  H01L21/768

    Abstract: A semiconductor structure includes a conductive feature disposed over a semiconductor substrate, a via disposed in a first interlayer dielectric (ILD) layer over the conductive feature, and a metal-containing etch-stop layer (ESL) disposed on the via, where the metal-containing ESL includes a first metal and is resistant to etching by a fluorine-containing etchant. The semiconductor structure further includes a conductive line disposed over the metal-containing ESL, where the conductive line includes a second metal different from the first metal and is etchable by the fluorine-containing etchant, and where the via is configured to interconnect the conductive line to the conductive feature. Furthermore, the semiconductor structure includes a second ILD layer disposed over the first ILD layer.

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