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公开(公告)号：US11050018B2
公开(公告)日：2021-06-29
申请号：US16664813
申请日：2019-10-26
发明人： Chih-Wei Lu , Hsi-Wen Tien , Wei-Hao Liao , David Dai , Chung-Ju Lee
摘要： A memory device includes a bottom electrode, a resistance switching element, a top electrode, a first spacer, and a metal-containing compound layer. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching element. The first spacer is disposed along a sidewall of the resistance switching element. The metal-containing compound layer is disposed along a sidewall of the first spacer, in which the first spacer is between the metal-containing compound layer and the resistance switching element.
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公开(公告)号：US11063213B2
公开(公告)日：2021-07-13
申请号：US16664815
申请日：2019-10-26
发明人： Chih-Wei Lu , Hsi-Wen Tien , Wei-Hao Liao , David Dai , Chung-Ju Lee
摘要： A method includes depositing a bottom electrode layer, a resistance switching element layer, and a top electrode layer over a first dielectric layer; etching the top electrode layer and the resistance switching element layer to form a resistance switching element over the bottom electrode layer and a top electrode over the resistance switching element; depositing a metal-containing compound layer over the top electrode, the resistance switching element, and the bottom electrode layer; and etching the metal-containing compound layer and the bottom electrode layer to form a bottom electrode over the first dielectric layer.
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公开(公告)号：US10461246B2
公开(公告)日：2019-10-29
申请号：US15706709
申请日：2017-09-16
发明人： Chih-Wei Lu , Hsi-Wen Tien , Wei-Hao Liao , David Dai , Chung-Ju Lee
摘要： A method for manufacturing a memory device is provided. The method includes forming a stack over a first portion of a bottom electrode layer, in which the stack comprises a resistance switching element and a top electrode over the resistance switching element; forming a first spacer around the resistance switching element; forming a penetration barrier layer around the resistance switching element; and removing a second portion of the bottom electrode layer using an etch operation, in which the penetration barrier layer has higher resistance to penetration of an etchant used in the etch operation than that of the first spacer.
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