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    Gate stacks with multiple high-κ dielectric layers
    71.
    发明授权
    Gate stacks with multiple high-κ dielectric layers 有权

    公开(公告)号：US11961895B2

    公开(公告)日：2024-04-16

    申请号：US17447109

    申请日：2021-09-08

    Applicant: International Business Machines Corporation

    Inventor： Ruqiang Bao ,  Ravikumar Ramachandran ,  Barry Linder ,  Shahab Siddiqui ,  Elnatan Mataev

    IPC: H01L29/49 ,  H01L29/40 ,  H01L29/51

    CPC classification number: H01L29/4966 ,  H01L29/401 ,  H01L29/513 ,  H01L29/517

    Abstract: A first semiconductor device includes an interfacial layer over a substrate, a first high-κ dielectric layer over the interfacial layer, a second high-κ dielectric layer over the first high-κ dielectric layer, a Ti—Si mixing layer over the second high-κ dielectric layer, and a gate electrode layer over the Ti—Si mixing layer. A second semiconductor device includes an interfacial layer over a substrate, a first high-κ dielectric layer over the interfacial layer, a Ti—Si mixing layer over the first high-κ dielectric layer, a second high-κ dielectric layer over the Ti—Si mixing layer, and a gate electrode layer over the second high-κ dielectric layer. The method includes forming an interfacial layer over a substrate, forming a first high-κ dielectric layer over the interfacial layer, forming a second high-κ dielectric layer over the first high-κ dielectric layer, and forming a gate electrode layer over the second high-κ dielectric layer.

    STACKED FET SRAM
    73.
    发明公开
    STACKED FET SRAM 审中-公开

    公开(公告)号：US20230345690A1

    公开(公告)日：2023-10-26

    申请号：US17660640

    申请日：2022-04-26

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Ruilong Xie ,  Carl Radens ,  Junli Wang ,  Ravikumar Ramachandran ,  Julien Frougier ,  Dechao Guo

    IPC: H01L27/11 ,  G11C11/412

    CPC classification number: H01L27/1104 ,  G11C11/412

    Abstract: Embodiments of present invention provide a SRAM device. The SRAM device includes a first, a second, and a third SRAM cell each having a first and a second pass-gate (PG) transistor, wherein the second PG transistor of the second SRAM cell and the first PG transistor of the first SRAM cell are stacked in a first PG transistor cell, and the first PG transistor of the third SRAM cell and the second PG transistor of the first SRAM cell are stacked in a second PG transistor cell. The first and second PG transistors of the first SRAM cell may be stacked on top of, or underneath, the second PG transistor of the second SRAM cell and/or the first PG transistor of the third SRAM cell.

    GATE STACKS WITH MULTIPLE HIGH-K DIELECTRIC LAYERS
    74.
    发明申请
    GATE STACKS WITH MULTIPLE HIGH-K DIELECTRIC LAYERS 有权

    公开(公告)号：US20230075740A1

    公开(公告)日：2023-03-09

    申请号：US17447109

    申请日：2021-09-08

    Applicant: International Business Machines Corporation

    Inventor： Ruqiang Bao ,  Ravikumar Ramachandran ,  Barry Linder ,  Shahab Siddiqui ,  Elnatan Mataev

    IPC: H01L29/49 ,  H01L29/40 ,  H01L29/51

    Abstract: A first semiconductor device includes an interfacial layer over a substrate, a first high-κ dielectric layer over the interfacial layer, a second high-κ dielectric layer over the first high-κ dielectric layer, a Ti—Si mixing layer over the second high-κ dielectric layer, and a gate electrode layer over the Ti—Si mixing layer. A second semiconductor device includes an interfacial layer over a substrate, a first high-κ dielectric layer over the interfacial layer, a Ti—Si mixing layer over the first high-κ dielectric layer, a second high-κ dielectric layer over the Ti—Si mixing layer, and a gate electrode layer over the second high-κ dielectric layer. The method includes forming an interfacial layer over a substrate, forming a first high-κ dielectric layer over the interfacial layer, forming a second high-κ dielectric layer over the first high-κ dielectric layer, and forming a gate electrode layer over the second high-κ dielectric layer.

    FinFET based ZRAM with convex channel region
    75.
    发明授权
    FinFET based ZRAM with convex channel region 有权

    公开(公告)号：US11139299B2

    公开(公告)日：2021-10-05

    申请号：US16444386

    申请日：2019-06-18

    Applicant: International Business Machines Corporation

    Inventor： Ravikumar Ramachandran ,  Reinaldo Ariel Vega

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/12 ,  H01L29/165 ,  H01L27/108

    Abstract: Embodiments of the present invention provide improved methods and structures for fabrication of capacitor-less DRAM devices, sometimes referred to as ZRAM devices. A channel is formed in a fin-type field effect transistor (finFET) that is comprised of a finned channel portion and a convex channel portion. The finned channel portion may be comprised of a first semiconductor material and the convex channel portion may be comprised of a second, different semiconductor material. In embodiments, a metal gate is disposed around the elongated surface of the channel region, but is not disposed on the short surface of the channel region. A first spacer is disposed adjacent to the gate and in direct physical contact with the short surface of the channel region, and a second spacer is disposed adjacent to the first spacer.

    Dynamic random access memory cell with self-aligned strap
    77.
    发明授权
    Dynamic random access memory cell with self-aligned strap 有权
    具有自对准带的动态随机存取存储单元

    公开(公告)号：US09564443B2

    公开(公告)日：2017-02-07

    申请号：US14158956

    申请日：2014-01-20

    Applicant: International Business Machines Corporation

    Inventor： John E. Barth, Jr. ,  Kangguo Cheng ,  Herbert L. Ho ,  Ali Khakifirooz ,  Ravikumar Ramachandran ,  Kern Rim ,  Reinaldo A. Vega

    IPC: H01L27/108 ,  H01L29/417 ,  H01L29/66

    CPC classification number: H01L27/10867 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/10879 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66181 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/785

    Abstract: After formation of trench capacitors and source and drain regions and gate structures for access transistors, a dielectric spacer is formed on a first sidewall of each source region, while a second sidewall of each source region and sidewalls of drain regions are physically exposed. Each dielectric spacer can be employed as an etch mask during removal of trench top dielectric portions to form strap cavities for forming strap structures. Optionally, selective deposition of a semiconductor material can be performed to form raised source and drain regions. In this case, the raised source regions grow only from the first sidewalls and do not grow from the second sidewalls. The raised source regions can be employed as a part of an etch mask during formation of the strap cavities. The strap structures are formed as self-aligned structures that are electrically isolated from adjacent access transistors by the dielectric spacers.

    Abstract translation: 在形成用于存取晶体管的沟槽电容器以及源极和漏极区域和栅极结构之后，在每个源极区域的第一侧壁上形成介电隔离物，同时物理地暴露每个源极区域的第二侧壁和漏极区域的侧壁。 在去除沟槽顶部电介质部分期间，可以使用每个电介质间隔物作为蚀刻掩模，以形成用于形成带状结构的带状空腔。 可选地，可以进行半导体材料的选择性沉积以形成凸起的源极和漏极区域。 在这种情况下，升高的源极区域仅从第一侧壁生长并且不从第二侧壁生长。 凸起的源极区域可以在形成带状空腔期间用作蚀刻掩模的一部分。 带状结构形成为通过电介质间隔物与相邻的存取晶体管电隔离的自对准结构。

    PROTECTION OF SEMICONDUCTOR-OXIDE-CONTAINING GATE DIELECTRIC DURING REPLACEMENT GATE FORMATION
    79.
    发明申请
    PROTECTION OF SEMICONDUCTOR-OXIDE-CONTAINING GATE DIELECTRIC DURING REPLACEMENT GATE FORMATION 有权
    在更换门窗形成过程中保护含半氧化物的含氧电介质

    公开(公告)号：US20160005735A1

    公开(公告)日：2016-01-07

    申请号：US14320760

    申请日：2014-07-01

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Gregory Costrini ,  Ravikumar Ramachandran ,  Reinaldo A. Vega ,  Richard S. Wise

    IPC: H01L27/088 ,  H01L29/51 ,  H01L29/06 ,  H01L21/311 ,  H01L21/306 ,  H01L21/308 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/762

    CPC classification number: H01L29/66545 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/517 ,  H01L29/6681

    Abstract: Semiconductor-oxide-containing gate dielectrics can be formed on surfaces of semiconductor fins prior to formation of a disposable gate structure. A high dielectric constant (high-k) dielectric spacer can be formed to protect each semiconductor-oxide-containing gate dielectric. Formation of the high-k dielectric spacers may be performed after formation of gate cavities by removal of disposable gate structures, or prior to formation of disposable gate structures. The high-k dielectric spacers can be used as protective layers during an anisotropic etch that vertically extends the gate cavity, and can be removed after vertical extension of the gate cavities. A subset of the semiconductor-oxide-containing gate dielectrics can be removed for formation of high-k gate dielectrics for first type devices, while another subset of the semiconductor-oxide-containing gate dielectrics can be employed as gate dielectrics for second type devices. The vertical extension of the gate cavities increases channel widths in the fin field effect transistors.

    Abstract translation: 在形成一次性栅极结构之前，可以在半导体鳍片的表面上形成含半导体氧化物的栅极电介质。 可以形成高介电常数（高k）电介质间隔物以保护每个含半导体氧化物的栅极电介质。 高k电介质间隔物的形成可以在通过移除一次性栅极结构或者在形成一次性栅极结构之前形成栅极空腔之后进行。 高k电介质间隔物可以在垂直延伸栅极腔的各向异性蚀刻期间用作保护层，并且可以在栅腔的垂直延伸之后被去除。 可以去除含半导体氧化物的栅极电介质的子集，以形成用于第一类型器件的高k栅极电介质，而含半导体氧化物的栅极电介质的另一子集可用作第二类型器件的栅极电介质。 栅极腔的垂直延伸增加了鳍状场效应晶体管中的沟道宽度。

    Fin field effect transistors having heteroepitaxial channels
    80.
    发明授权
    Fin field effect transistors having heteroepitaxial channels 有权
    Fin场效应晶体管具有异质外延通道

    公开(公告)号：US09190406B2

    公开(公告)日：2015-11-17

    申请号：US14158987

    申请日：2014-01-20

    Applicant: International Business Machines Corporation

    Inventor： Emre Alptekin ,  Wing L. Lai ,  Ravikumar Ramachandran ,  Matthew W. Stoker ,  Henry K. Utomo ,  Reinaldo A. Vega

    IPC: H01L21/00 ,  H01L29/66 ,  H01L27/088 ,  H01L21/306 ,  H01L21/8234 ,  H01L29/06

    CPC classification number: H01L27/0886 ,  H01L21/30604 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/6681

    Abstract: Disposable gate structures are formed over semiconductor material portions, and source and drain regions can be formed in the semiconductor material portions. After formation of a planarization dielectric layer, one type of disposable gate structure can be removed selective to at least another type of disposable gate structure employing a patterned hard dielectric mask layer. After recessing a surface portion of a body portion, a heteroepitaxial channel portion is formed on the remaining physically exposed portion of the body portion by selective epitaxy of a semiconductor material different from the semiconductor material of the remaining body portion. A plurality of types of heteroepitaxial channel portions can be formed in different types of semiconductor devices. Replacement gate structures can be formed in the gate cavities to provide field effect transistors having different threshold voltages.

    Abstract translation: 在半导体材料部分上形成一次性栅极结构，并且可以在半导体材料部分中形成源极和漏极区域。 在形成平坦化介电层之后，可以选择性地去除一种类型的一次性栅极结构至少使用图案化的硬介电掩模层的另一种类型的一次性栅极结构。 在凹陷主体部分的表面部分之后，通过选择性地外延不同于剩余主体部分的半导体材料的半导体材料，在主体部分的剩余物理暴露部分上形成异质外延通道部分。 可以在不同类型的半导体器件中形成多种类型的异质外延沟道部分。 可以在栅极腔中形成替代栅极结构，以提供具有不同阈值电压的场效应晶体管。

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