公开(公告)号：US07772581B2

公开(公告)日：2010-08-10

申请号：US11530625

申请日：2006-09-11

申请人： Hsiang-Lan Lung

发明人： Hsiang-Lan Lung

IPC分类号： H01L29/04

CPC分类号： H01L45/06 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1675

摘要： A memory cell device of the type that includes a memory material switchable between electrical property states by application of energy, situated between first and second (“bottom” and “top”) electrodes has a top electrode including a larger body portion and a stem portion. The memory material is disposed as a layer over a bottom electrode layer, and a base of the stem portion of the top electrode is in electrical contact with a small area of the surface of the memory material. Methods for making the memory cell are described.

摘要翻译： 位于第一和第二（“底部”和“顶部”）电极之间的包括可通过施加能量在电性能状态之间切换的存储材料的类型的存储单元装置具有包括较大主体部分和杆部分的顶部电极 。 记忆材料被设置在底部电极层上的一层，并且顶部电极的杆部的基部与存储材料的表面的小区域电接触。 描述制造存储器单元的方法。

公开(公告)号：US20100133500A1

公开(公告)日：2010-06-03

申请号：US12647349

申请日：2009-12-24

申请人： Hsiang-Lan Lung

发明人： Hsiang-Lan Lung

IPC分类号： H01L45/00

CPC分类号： H01L45/122 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/144 ,  H01L45/1625

摘要： Memory cells are described along with methods for manufacturing. A memory cell as described herein includes a bottom electrode, a memory element and a side electrode. The bottom electrode contacts the memory element at a first contact surface on the bottom of the memory element. The side electrode contacts the memory element at a second contact surface on the side of the memory element, where the second contact surface on the side faces laterally relative to the first contact surface on the bottom.

摘要翻译： 描述存储单元以及制造方法。 如本文所述的存储单元包括底电极，存储元件和侧电极。 底部电极在存储元件底部的第一接触表面处接触存储元件。 侧电极在存储元件一侧的第二接触表面处接触存储元件，其中侧面上的第二接触表面相对于底部上的第一接触表面横向。

公开(公告)号：US07683360B2

公开(公告)日：2010-03-23

申请号：US11378904

申请日：2006-03-17

申请人： Yi-Chou Chen ,  Hsiang-Lan Lung ,  Ruichen Liu

发明人： Yi-Chou Chen ,  Hsiang-Lan Lung ,  Ruichen Liu

IPC分类号： H01L29/04

CPC分类号： H01L45/06 ,  G11C13/0004 ,  H01L27/2463 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/1691

摘要： A memory cell structure includes a substrate having a bottom electrode at least partially disposed within the substrate; a pad disposed at least partially over the substrate; a phase change element having a chalcogenide material, disposed at least partially over the substrate and adjacent to the pad, the phase change element being adjacent and operatively coupled to the bottom electrode; and a top electrode operatively coupled to the phase change element. Moreover, the pad is formed by a method including depositing a first material layer over the substrate, etching the first material layer to form a pad strip and to expose the bottom electrode, and etching the pad strip to from the pad.

摘要翻译： 存储单元结构包括具有至少部分地设置在基板内的底电极的基板; 至少部分地设置在所述基板上的垫; 具有硫族化物材料的相变元件，至少部分地设置在所述衬底上并且与所述焊盘相邻，所述相变元件邻近并且可操作地耦合到所述底部电极; 以及可操作地耦合到相变元件的顶部电极。 此外，衬垫通过包括在衬底上沉积第一材料层的方法形成，蚀刻第一材料层以形成焊盘条并暴露底部电极，以及将焊盘条从焊盘蚀刻。

公开(公告)号：US07638855B2

公开(公告)日：2009-12-29

申请号：US11123589

申请日：2005-05-06

申请人： Hsiang-Lan Lung

发明人： Hsiang-Lan Lung

IPC分类号： H01L29/00

CPC分类号： G11C17/00 ,  H01L23/5252 ,  H01L27/1021 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An anti-fuse one-time-programmable (OTP) nonvolatile memory cell has a P well substrate with two P− doped regions. Another N+ doped region, functioning as a bit line, is positioned adjacent and between the two P− doped regions on the substrate. An anti-fuse is defined over the N+ doped region. Two insulator regions are deposited over the two P− doped regions. An impurity doped polysilicon layer is defined over the two insulator regions and the anti-fuse. A polycide layer is defined over the impurity doped polysilicon layer. The polycide layer and the polysilicon layer function as a word line. A programmed region, i.e., a link, functioning as a diode, is formed on the anti-fuse after the anti-fuse OTP nonvolatile memory cell is programmed. The array structure of anti-fuse OTP nonvolatile memory cells and methods for programming, reading, and fabricating such a cell are also disclosed.

摘要翻译： 反熔丝一次可编程（OTP）非易失性存储单元具有具有两个P-掺杂区域的P阱衬底。 作为位线起作用的另一个N +掺杂区位于衬底上的两个P-掺杂区之间。 反熔丝定义在N +掺杂区域上。 在两个P掺杂区域上沉积两个绝缘体区域。 在两个绝缘体区域和反熔丝上限定杂质掺杂多晶硅层。 在杂质掺杂多晶硅层上限定多晶硅化物层。 多晶硅层和多晶硅层用作字线。 在反熔丝OTP非易失性存储单元被编程之后，在反熔丝上形成用作二极管的编程区域，即链路。 还公开了反熔丝OTP非易失性存储单元的阵列结构以及用于编程，读取和制造这种单元的方法。

公开(公告)号：US20090268507A1

公开(公告)日：2009-10-29

申请号：US12111258

申请日：2008-04-29

申请人： Matthew J. Breitwisch ,  Chung H. Lam ,  Hsiang-Lan Lung ,  Bipin Rajendran ,  Alejandro G. Schrott ,  Yu Zhu

发明人： Matthew J. Breitwisch ,  Chung H. Lam ,  Hsiang-Lan Lung ,  Bipin Rajendran ,  Alejandro G. Schrott ,  Yu Zhu

IPC分类号： G11C11/00 ,  H01S4/00

CPC分类号： H01L45/144 ,  G11C13/0004 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  Y10T29/49002

摘要： A phase change memory control ring lower electrode is disclosed. The lower electrode includes an outer ring electrode in thermal contact with a phase change memory element, an inner seed layer disposed within the outer ring electrode and in contact with the phase change memory element, and an electrically conductive bottom layer coupled to the outer ring electrode.

摘要翻译： 公开了一种相变存储器控制环下电极。 下电极包括与相变存储元件热接触的外环电极，设置在外环电极内并与相变存储元件接触的内种子层，以及耦合到外环电极的导电底层 。

公开(公告)号：US20090200534A1

公开(公告)日：2009-08-13

申请号：US12027675

申请日：2008-02-07

申请人： Bipin Rajendran ,  Thomas Happ ,  Hsiang-Lan Lung ,  Min Yang

发明人： Bipin Rajendran ,  Thomas Happ ,  Hsiang-Lan Lung ,  Min Yang

IPC分类号： H01L47/00 ,  H01L21/36

CPC分类号： H01L27/24 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02645 ,  H01L21/02667 ,  H01L27/1021 ,  H01L29/8613

摘要： The present invention, in one embodiment, provides a method of producing a PN junction the method including at least the steps of providing a Si-containing substrate; forming an insulating layer on the Si-containing substrate; forming a via through the insulating layer to expose at least a portion of the Si-containing substrate; forming a seed layer of the exposed portion of the Si containing substrate; forming amorphous Si on at least the seed layer; converting at least a portion of the amorphous Si to provide crystalline Si; and forming a first dopant region abutting a second dopant region in the crystalline Si.

摘要翻译： 本发明在一个实施方案中提供了一种制备PN结的方法，所述方法至少包括提供含Si衬底的步骤; 在含Si衬底上形成绝缘层; 通过所述绝缘层形成通孔以露出所述含Si衬底的至少一部分; 形成含Si衬底的暴露部分的种子层; 在至少种子层上形成非晶态Si; 转化至少一部分非晶Si以提供晶体Si; 以及形成邻接所述晶体Si中的第二掺杂区的第一掺杂区。

公开(公告)号：US07569844B2

公开(公告)日：2009-08-04

申请号：US11736384

申请日：2007-04-17

申请人： Hsiang-Lan Lung

发明人： Hsiang-Lan Lung

IPC分类号： H01L29/02 ,  H01L21/00 ,  G11C11/56

CPC分类号： H01L45/122 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1683 ,  Y10S438/90

摘要： A memory cell includes a memory cell layer over a memory cell access layer. The memory cell access layer comprises a bottom electrode. The memory cell layer comprises a dielectric layer and a side electrode at least partially defining a void with a memory element therein. The memory element comprises a memory material switchable between electrical property states by the application of energy. The memory element is in electrical contact with the side electrode and with the bottom electrode. In some examples the memory element has a pillar shape with a generally constant lateral dimension with the side electrode and the dielectric layer surrounding and in contact with first and second portions of the memory element.

摘要翻译： 存储单元包括存储单元接入层上的存储单元层。 存储单元访问层包括底电极。 存储单元层包括电介质层和至少部分地限定其中具有存储元件的空隙的侧电极。 存储元件包括通过施加能量在电性能状态之间切换的存储器材料。 存储元件与侧电极和底电极电接触。 在一些示例中，存储元件具有大致恒定的横向尺寸的支柱形状，其中侧面电极和介电层围绕并与存储元件的第一和第二部分接触。

公开(公告)号：US20090176354A1

公开(公告)日：2009-07-09

申请号：US11970100

申请日：2008-01-07

申请人： Bipin Rajendran ,  Thomas Happ ,  Hsiang-Lan Lung

发明人： Bipin Rajendran ,  Thomas Happ ,  Hsiang-Lan Lung

IPC分类号： H01L21/20

CPC分类号： H01L21/02675 ,  H01L21/02532 ,  H01L21/02689 ,  H01L27/1021 ,  H01L27/24 ,  H01L29/8613

摘要： The present invention, in one embodiment, provides a method of producing a PN junction the method including providing a single crystal substrate; forming an insulating layer on the single crystal substrate; forming a via through the insulating layer to provide an exposed portion of the single crystal substrate; forming amorphous Si on at least the exposed portion of the single crystal substrate; converting at least a portion of the amorphous Si into single crystal Si; and forming dopant regions in the single crystal Si. In one embodiment the diode of the present invention is integrated with a memory device.

摘要翻译： 本发明在一个实施例中提供了一种制造PN结的方法，该方法包括提供单晶衬底; 在单晶基板上形成绝缘层; 通过所述绝缘层形成通孔以提供所述单晶衬底的暴露部分; 在单晶衬底的至少暴露部分上形成非晶Si; 将至少一部分非晶Si转化为单晶Si; 并在单晶Si中形成掺杂区。 在一个实施例中，本发明的二极管与存储器件集成。

公开(公告)号：US07515461B2

公开(公告)日：2009-04-07

申请号：US11620432

申请日：2007-01-05

申请人： Thomas D. Happ ,  Hsiang-Lan Lung ,  Thomas Nirschl

发明人： Thomas D. Happ ,  Hsiang-Lan Lung ,  Thomas Nirschl

IPC分类号： G11C11/00 ,  G11C7/10 ,  G11C7/02

CPC分类号： G11C13/004 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2013/0054 ,  G11C2213/79

摘要： A memory device and a method of reading the same includes a phase change element having a data state associated therewith that features maintaining the consistency of the data state of the phase change element in the presence of a read current. The memory circuit includes a sense amplifier that defines a sensing node. Circuitry selectively places the bit line in data communication with the sensing node, defining a selected bit line. A current source produces a read current, and a switch selectively applies the read current to the sensing node. Logic is in electrical communication with the sensing node to control the total energy to which the phase change material is subjected in the presence of the read current so that the data state remains consistent.

摘要翻译： 存储器件及其读取方法包括具有与其相关联的数据状态的相变元件，其特征在于存在读取电流时维持相变单元的数据状态的一致性。 存储器电路包括限定感测节点的读出放大器。 电路选择性地将位线与感测节点进行数据通信，定义所选择的位线。 电流源产生读取电流，并且开关选择性地将读取电流施加到感测节点。 逻辑与感测节点电气通信，以在存在读取电流的情况下控制相变材料经受的总能量，使得数据状态保持一致。

公开(公告)号：US20090057641A1

公开(公告)日：2009-03-05

申请号：US12266200

申请日：2008-11-06

申请人： Hsiang-Lan Lung

发明人： Hsiang-Lan Lung

IPC分类号： H01L45/00

CPC分类号： G11C8/08 ,  G11C8/10 ,  G11C13/0004 ,  G11C13/0028 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/165 ,  H01L45/1675 ,  H01L45/1691

摘要： A phase change memory cell includes first and second electrodes having generally coplanar surfaces spaced apart by a gap and a phase change bridge electrically coupling the first and second electrodes. The phase change bridge may extend over the generally coplanar surfaces and across the gap. The phase change bridge has a higher transition temperature bridge portion and a lower transition temperature portion. The lower transition temperature portion comprises a phase change region which can be transitioned from generally crystalline to generally amorphous states at a lower temperature than the higher transition temperature portion. A method for making a phase change memory cell is also disclosed.

摘要翻译： 相变存储单元包括具有通过间隙间隔开的大致共面的第一和第二电极以及电耦合第一和第二电极的相变桥。 相变桥可以在大致共面的表面上并跨越间隙延伸。 相变桥具有较高的转变温度桥接部分和较低的转变温度部分。 较低的转变温度部分包括可在比较高转变温度部分低的温度下从一般结晶转变为通常非晶态的相变区。 还公开了一种制造相变存储单元的方法。