公开(公告)号：US20080153217A1

公开(公告)日：2008-06-26

申请号：US11616147

申请日：2006-12-26

Applicant: Deleep R. Nair ,  Christopher V. Baiocco ,  Xiangdong Chen ,  Junjung Kim ,  Jae-eun Park ,  Daewon Yang

Inventor： Deleep R. Nair ,  Christopher V. Baiocco ,  Xiangdong Chen ,  Junjung Kim ,  Jae-eun Park ,  Daewon Yang

IPC: H01L21/8234 ,  H01L21/336

CPC classification number: H01L29/7843 ,  H01L21/31604 ,  H01L29/66575

Abstract: A method of producing a metal oxide semiconductor field effect transistor (MOSFET) creates a transistor by patterning a gate structure over a substrate, forming spacers on sides of the gate structure, and forming conductor regions within the substrate on alternate sides of the gate stack. The gate structure and the conductor regions make up the transistor. In order to reduce high power plasma induced damage, the method initially applies a first plasma having a first power level to the transistor to form a first stress layer over the transistor. After the first lower-power plasma is applied, the method then applies a second plasma having a second power level to the transistor to from a second stress layer over the first stress layer. The second power level is higher (e.g., at least 5 times higher) than the first power level.

Abstract translation: 制造金属氧化物半导体场效应晶体管（MOSFET）的方法通过在衬底上图案化栅极结构来形成晶体管，在栅极结构的侧面上形成间隔物，以及在栅极堆叠的另一侧上在衬底内形成导体区域。 栅极结构和导体区域构成晶体管。 为了减少高功率等离子体引起的损伤，该方法首先将具有第一功率电平的第一等离子体施加到晶体管，以在晶体管上形成第一应力层。 在施加第一低功率等离子体之后，该方法然后将第二等离子体具有第二功率电平施加到第一应力层上的第二应力层至晶体管。 第二功率电平比第一功率电平高（例如，至少高5倍）。

公开(公告)号：US20080124880A1

公开(公告)日：2008-05-29

申请号：US11534651

申请日：2006-09-23

Applicant: Wenhe Lin ,  Randy William Mann ,  Padraic C. Shafer ,  Christopher Vincent Baiocco ,  Zhijoing Luo ,  Haining S. Yang ,  Xiangdong Chen

Inventor： Wenhe Lin ,  Randy William Mann ,  Padraic C. Shafer ,  Christopher Vincent Baiocco ,  Zhijoing Luo ,  Haining S. Yang ,  Xiangdong Chen

IPC: H01L21/336

CPC classification number: H01L29/6659 ,  H01L29/6653 ,  H01L29/7833 ,  H01L29/7843

Abstract: Some non-limiting example embodiments comprise a disposable spacer formation and removal process and a stress capping layer process. We provide a gate structure over a substrate. We form disposable spacers abutting the at least one gate sidewall. We form S/D regions adjacent the disposable spacers. We remove the disposable spacers. We can form silicide regions over the S/D and gate. In an aspect, we can deposit a stress inducing layer over the gate and surface portions of the substrate adjacent to the gate, wherein the stress inducing liner provides a stress to a portion of the substrate underlying the gate electrode.

Abstract translation: 一些非限制性示例性实施例包括一次性间隔物形成和移除过程以及应力覆盖层过程。 我们在衬底上提供栅极结构。 我们形成邻接至少一个栅极侧壁的一次性间隔物。 我们在一次性间隔物附近形成S / D区域。 我们取出一次性垫片。 我们可以在S / D和门上形成硅化物区域。 在一方面，我们可以在邻近栅极的基板的栅极和表面部分上沉积应力诱导层，其中应力诱导衬垫向栅电极下方的衬底的一部分提供应力。

公开(公告)号：US20080085585A1

公开(公告)日：2008-04-10

申请号：US11538850

申请日：2006-10-05

Applicant: Haining Yang ,  Xiangdong Chen

Inventor： Haining Yang ,  Xiangdong Chen

IPC: H01L21/336

CPC classification number: H01L21/823835 ,  H01L21/823842 ,  H01L27/092

Abstract: The invention is directed to an improved transistor that reduces dopant cross-diffusion and improves chip density. A first embodiment of the invention comprises gate electrode material partially removed at a junction of a first gate electrode region comprised of gate material doped with first ions for a first device and second gate electrode region comprised of gate material doped with second ions for a second device. The respectively doped regions are connected by a silicide layer near the top surface of the gate conductors.

Abstract translation: 本发明涉及减少掺杂剂交叉扩散并改善芯片密度的改进的晶体管。 本发明的第一实施例包括在由掺杂有用于第一器件的第一离子的栅极材料构成的第一栅极电极区域和由掺杂有第二离子的栅极材料构成的第二栅极电极区域的第一栅极电极区域处部分去除的栅电极材料，用于第二器件 。 分别掺杂的区域通过靠近栅极导体的顶表面的硅化物层连接。

公开(公告)号：US20070181980A1

公开(公告)日：2007-08-09

申请号：US11307481

申请日：2006-02-09

Applicant: Thomas Dyer ,  Xiangdong Chen ,  James Toomey ,  Haining Yang

Inventor： Thomas Dyer ,  Xiangdong Chen ,  James Toomey ,  Haining Yang

IPC: H01L29/04

CPC classification number: H01L21/823807 ,  H01L21/82385 ,  H01L21/823857

Abstract: The present invention relates to a semiconductor substrate comprising at least first and second device regions, wherein the first device region comprises a first recess having interior surfaces oriented along a first set of equivalent crystal planes, and wherein the second device region comprises a second recess having interior surfaces oriented along a second, different set of equivalent crystal planes. A semiconductor device structure can be formed using such a semiconductor substrate. Specifically, at least one n-channel field effect transistor (n-FET) can be formed at the first device region, which comprises a channel that extends along the interior surfaces of the first recess. At least one p-channel field effect transistor (p-FET) can be formed at the second device region, which comprises a channel that extends along the interior surfaces of the second recess.

Abstract translation: 本发明涉及包括至少第一和第二器件区域的半导体衬底，其中第一器件区域包括具有沿着第一组等效晶面取向的内表面的第一凹槽，并且其中第二器件区域包括第二凹部， 沿着第二不同组的等效晶面取向的内表面。 可以使用这种半导体衬底形成半导体器件结构。 具体而言，可以在第一器件区域形成至少一个n沟道场效应晶体管（n-FET），该第一器件区域包括沿着第一凹槽的内表面延伸的沟道。 至少一个p沟道场效应晶体管（p-FET）可以在第二器件区域形成，该第二器件区域包括沿着第二凹槽的内表面延伸的沟道。

公开(公告)号：US20070178650A1

公开(公告)日：2007-08-02

申请号：US11307331

申请日：2006-02-01

Applicant: Xiangdong Chen ,  Haining Yang

Inventor： Xiangdong Chen ,  Haining Yang

IPC: H01L21/336

CPC classification number: H01L29/78 ,  H01L29/165 ,  H01L29/66356 ,  H01L29/7391

Abstract: The present invention relates to a heterojunction tunneling effect transistor (TFET), which comprises spaced apart source and drain regions with a channel region located therebetween and a gate stack located over the channel region. The drain region comprises a first semiconductor material and is doped with a first dopant species of a first conductivity type. The source region comprises a second, different semiconductor material and is doped with a second dopant species of a second, different conductivity type. The gate stack comprises at least a gate dielectric and a gate conductor. When the heterojunction TFET is an n-channel TFET, the drain region comprises n-doped silicon, while the source region comprises p-doped silicon germanium. When the heterojunction TFET is a p-channel TFET, the drain region comprises p-doped silicon, while the source region comprises n-doped silicon carbide.

Abstract translation: 本发明涉及异质结隧道效应晶体管（TFET），其包括间隔开的源极和漏极区，其中位于其间的沟道区和位于沟道区上方的栅极叠层。 漏极区域包括第一半导体材料并且掺杂有第一导电类型的第一掺杂物种类。 源区包括第二不同的半导体材料，并且掺杂有第二不同导电类型的第二掺杂物种。 栅极堆叠至少包括栅极电介质和栅极导体。 当异质结TFET是n沟道TFET时，漏极区域包括n掺杂的硅，而源极区域包括p掺杂的硅锗。 当异质结TFET是p沟道TFET时，漏极区包括p掺杂的硅，而源区包括n掺杂的碳化硅。

公开(公告)号：US07104250B1

公开(公告)日：2006-09-12

申请号：US11162248

申请日：2005-09-02

Applicant: Jianwen Yi ,  Huiyu Fu ,  Xiangdong Chen ,  Zhiyu Han

Inventor： Jianwen Yi ,  Huiyu Fu ,  Xiangdong Chen ,  Zhiyu Han

IPC: F02B1/00 ,  F02B5/00

CPC classification number: F02M69/045 ,  F02B17/005 ,  F02M61/1806 ,  Y02T10/128

Abstract: A system and method for controlling combustion in a direct injection spark ignition internal combustion engine inject fuel directly into a combustion chamber through an injector having an ignition jet or group of jets positioned primarily to support stratified charge formation and a mixing jet or group of jets positioned primarily to support homogeneous charge formation. The ignition jet(s) and mixing jet(s) produce discernibly different yet well connected fuel clouds within the cylinder to provide stable combustion and reduce cylinder wall wetting by appropriate selection of the axial/longitudinal angles and radial/circumferential angles of the ignition and mixing jets.

Abstract translation: 用于控制直接喷射火花点火内燃机中的燃烧的系统和方法通过具有主要用于支撑分层电荷形成的点火射流或射流组的喷射器将燃料直接喷射到燃烧室中，喷射器或喷射器组被定位 主要用于支持均匀电荷形成。 点火喷气和混合射流在气缸内产生明显不同但良好连接的燃料云，以通过适当选择点火的轴向/纵向角度和径向/圆周角度来提供稳定的燃烧并减少气缸壁润湿， 混合喷气机

公开(公告)号：US07002209B2

公开(公告)日：2006-02-21

申请号：US10851830

申请日：2004-05-21

Applicant: Xiangdong Chen ,  Dureseti Chidambarrao ,  Oleg Gluschenkov ,  Brian Greene ,  Kern Rim ,  Haining S. Yang

Inventor： Xiangdong Chen ,  Dureseti Chidambarrao ,  Oleg Gluschenkov ,  Brian Greene ,  Kern Rim ,  Haining S. Yang

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present invention provides a semiconducting device including at least one gate region including a gate conductor located on a surface of a substrate, the substrate having an exposed surface adjacent the gate region; a silicide contact located adjacent the exposed surface; and a stress inducing liner located on the silicide contact, the exposed surface of the substrate adjacent to the gate region and the at least one gate region, wherein the stress inducing liner provides a stress to a device channel portion of the substrate underlying the gate region. The stress produced on the device channel is a longitudinal stress on the order of about 200 MPa to about 2000 MPa. The present invention also provides a method for forming the above-described semiconducting device.

Abstract translation: 本发明提供了一种半导体器件，其包括至少一个栅极区域，该栅极区域包括位于衬底表面上的栅极导体，该衬底具有邻近栅极区域的暴露表面; 位于暴露表面附近的硅化物触点; 以及位于所述硅化物接触处的所述应力诱导衬垫，所述衬底的与所述栅极区域和所述至少一个栅极区域相邻的暴露表面，其中所述应力诱导衬垫向所述栅极区域下方的衬底的器件沟道部分施加应力 。 在器件通道上产生的应力是约200MPa至约2000MPa的纵向应力。 本发明还提供了形成上述半导体器件的方法。

公开(公告)号：US06972461B1

公开(公告)日：2005-12-06

申请号：US10710274

申请日：2004-06-30

Applicant: Xiangdong Chen ,  Dureseti Chidambarrao ,  Geng Wang ,  Huilong Zhu

Inventor： Xiangdong Chen ,  Dureseti Chidambarrao ,  Geng Wang ,  Huilong Zhu

IPC: H01L21/336 ,  H01L21/8244 ,  H01L27/01 ,  H01L27/11 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L27/11 ,  H01L27/1108 ,  H01L29/66795 ,  H01L29/78687 ,  Y10S438/933

Abstract: A structure for use as a MOSFET employs an SOI wafer with a SiGe island resting on the SOI layer and extending between two blocks that serve as source and drain; epitaxially grown Si on the vertical surfaces of the SiGe forms the transistor channel. The lattice structure of the SiGe is arranged such that the epitaxial Si has little or no strain in the direction between the S and D and a significant strain perpendicular to that direction.

Abstract translation: 用作MOSFET的结构采用具有SiGe岛的SOI晶片，其位于SOI层上并在用作源极和漏极的两个块之间延伸; 在SiGe的垂直表面上外延生长的Si形成晶体管沟道。 SiGe的晶格结构被布置成使得外延Si在S和D之间的方向上几乎没有或没有应变，并且垂直于该方向的显着应变。

公开(公告)号：US20050260808A1

公开(公告)日：2005-11-24

申请号：US10851830

申请日：2004-05-21

Applicant: Xiangdong Chen ,  Dureseti Chidambarrao ,  Oleg Gluschenkov ,  Brian Greene ,  Kern Rim ,  Haining Yang

Inventor： Xiangdong Chen ,  Dureseti Chidambarrao ,  Oleg Gluschenkov ,  Brian Greene ,  Kern Rim ,  Haining Yang

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present invention provides a semiconducting device including at least one gate region including a gate conductor located on a surface of a substrate, the substrate having an exposed surface adjacent the gate region; a silicide contact located adjacent the exposed surface; and a stress inducing liner located on the silicide contact, the exposed surface of the substrate adjacent to the gate region and the at least one gate region, wherein the stress inducing liner provides a stress to a device channel portion of the substrate underlying the gate region. The stress produced on the device channel is a longitudinal stress on the order of about 200 MPa to about 2000 MPa. The present invention also provides a method for forming the above-described semiconducting device.

Abstract translation: 本发明提供了一种半导体器件，其包括至少一个栅极区域，该栅极区域包括位于衬底表面上的栅极导体，该衬底具有邻近栅极区域的暴露表面; 位于暴露表面附近的硅化物触点; 以及位于所述硅化物接触处的所述应力诱导衬垫，所述衬底的与所述栅极区域和所述至少一个栅极区域相邻的暴露表面，其中所述应力诱导衬垫向所述栅极区域下方的衬底的器件沟道部分施加应力 。 在器件通道上产生的应力是约200MPa至约2000MPa的纵向应力。 本发明还提供了形成上述半导体器件的方法。

公开(公告)号：US20050093021A1

公开(公告)日：2005-05-05

申请号：US10698122

申请日：2003-10-31

Applicant: Qiqing Ouyang ,  Xiangdong Chen

Inventor： Qiqing Ouyang ,  Xiangdong Chen

IPC: H01L27/08 ,  H01L21/20 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/78 ,  H01L29/786 ,  H01L29/739

CPC classification number: H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/7841

Abstract: A structure, and method of fabrication, for high performance field effect devices is disclosed. The MOS structures include a crystalline Si body of one conductivity type, a strained SiGe layer epitaxially grown on the Si body serving as a buried channel for holes, a Si layer epitaxially grown on the SiGe layer serving as a surface channel for electrons, and a source and a drain containing an epitaxially deposited, strained SiGe of opposing conductivity type than the Si body. The SiGe source/drain forms a heterojunction and a metallurgical junction with the Si body that coincide with each other with a tolerance of less than about 10 nm, and preferably less than about 5 nm. The heterostructure source/drain is instrumental in reducing short channel effects. These structures are especially advantageous for PMOS due to increased hole mobility in the compressively strained SiGe channel. Representative embodiments include CMOS structures on bulk and on SOI.

Abstract translation: 公开了一种用于高性能场效应器件的结构和制造方法。 MOS结构包括一种导电类型的晶体Si体，在用作空穴的掩埋沟道的Si体上外延生长的应变SiGe层，在用作电子的表面通道的SiGe层上外延生长的Si层，以及 源极和漏极，其包含与Si体相反的导电类型的外延沉积的应变SiGe。 SiGe源极/漏极与Si体形成异质结和冶金结，其彼此重合，具有小于约10nm，优选小于约5nm的公差。 异质结构源/漏极有助于减少短沟道效应。 由于在压缩应变SiGe通道中空穴迁移率增加，这些结构对于PMOS是特别有利的。 代表性的实施例包括在本体上和在SOI上的CMOS结构。