公开(公告)号：US4658379A

公开(公告)日：1987-04-14

申请号：US666380

申请日：1984-10-30

Applicant: Kazuyasu Fujishima ,  Kazuhiro Shimotori ,  Hideyuki Ozaki ,  Hideshi Miyatake ,  Masahiro Tomisato

Inventor： Kazuyasu Fujishima ,  Kazuhiro Shimotori ,  Hideyuki Ozaki ,  Hideshi Miyatake ,  Masahiro Tomisato

IPC: G11C8/10 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC classification number: G11C29/787 ,  G11C8/10

Abstract: A semiconductor memory device with a laser programmable redundancy circuit, which includes: a plurality of decoders for selecting a row or column of the memory; at least one spare decoder which is selected instead of a decoder connected to a faulty memory cell; a link element inserted in series with the precharging transistor and connected between the power supply and the decoder output line; a signal generator which generates a non-selection signal for making the object decoder unselected only when a spare decoder is selected, the signal generator being provided in the spare decoder; and a transistor, having a gate to which the non-selection signal is input, with the drain and the source thereof being connected to the decoder output and ground, respectively, the transistor being provided in the decoder.

Abstract translation: 一种具有激光可编程冗余电路的半导体存储器件，包括：多个解码器，用于选择存储器的行或列; 选择代替连接到故障存储器单元的解码器的至少一个备用解码器; 与预充电晶体管串联插入并连接在电源和解码器输出线之间的连接元件; 信号发生器，其仅在选择了备用解码器时产生用于使对象解码器未选择的非选择信号，所述信号发生器设置在所述备用解码器中; 以及晶体管，其具有输入非选择信号的栅极，漏极和源极分别连接到解码器输出和接地，晶体管分别设置在解码器中。

公开(公告)号：US4593382A

公开(公告)日：1986-06-03

申请号：US418911

申请日：1982-09-16

Applicant: Kazuyasu Fujishima ,  Kazuhiro Shimotori ,  Hideyuki Ozaki ,  Takao Nakano

Inventor： Kazuyasu Fujishima ,  Kazuhiro Shimotori ,  Hideyuki Ozaki ,  Takao Nakano

IPC: H01L29/78 ,  G11C11/404 ,  H01L27/10 ,  G11C11/24

CPC classification number: G11C11/404

Abstract: An MOS dynamic memory device is improved in operation by adding a cell plate voltage control circuit to terminals of the word lines and connected to respective cell plates. In operation, the cell plate is recharged after discharged during with a time which a word line remains driven.

Abstract translation: 通过将单元板电压控制电路添加到字线的端子并连接到各个单元板，从而改善了MOS动态存储器件的工作。 在操作中，单元板在放电之后被充电，同时字线保持驱动的时间。

公开(公告)号：US4586167A

公开(公告)日：1986-04-29

申请号：US568138

申请日：1984-01-04

Applicant: Kazuyasu Fujishima ,  Kazuhiro Shimotori ,  Hideyuki Ozaki ,  Hideshi Miyatake

Inventor： Kazuyasu Fujishima ,  Kazuhiro Shimotori ,  Hideyuki Ozaki ,  Hideshi Miyatake

IPC: G11C7/10 ,  G11C7/22 ,  G11C8/18 ,  G11C13/00

CPC classification number: G11C7/1045 ,  G11C7/22 ,  G11C8/18

Abstract: Disclosed is a semiconductor memory device which is operable in a selected one of page mode and nibble mode, depending upon the length of time in which an external column address strobe signal stays at a specific level. The semiconductor memory device comprises a circuit for discriminating the length of time where the external column address strobe signal is at a specific level with a predetermined period of time. Data is outputted in page mode in response to one of results of such discrimination and in nibble mode in response to the other result of the discrimination. The discriminating circuit may comprise a second internal column address strobe signal generator and a delay circuit. The second internal column address strobe signal generator includes a NAND circuit at its first stage, and the delay circuit is designed to have different delay times at the building-up and downward edges of an input signal applied thereto. The output of the discriminator is used to operate and reset an output circuit whereby one of the output modes is selected.

Abstract translation: 公开了根据外部列地址选通信号保持在特定级别的时间长度，可以在页模式和半字节模式中选择的一个中操作的半导体存储器件。 半导体存储器件包括用于在预定时间段内鉴别外部列地址选通信号处于特定电平的时间长度的电路。 响应于这种歧视的结果之一，以页面模式输出数据，并且响应于歧视的另一结果，以半字节模式输出数据。 识别电路可以包括第二内部列地址选通信号发生器和延迟电路。 第二内部列地址选通信号发生器包括在其第一级的NAND电路，并且延迟电路被设计为在施加到其的输入信号的建立和向下边缘处具有不同的延迟时间。 鉴别器的输出用于操作和复位输出电路，由此选择一个输出模式。

公开(公告)号：US06414883B2

公开(公告)日：2002-07-02

申请号：US09860795

申请日：2001-05-21

Applicant: Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

Inventor： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

IPC: G11C700

CPC classification number: G11C11/4085 ,  G11C5/14 ,  G11C5/147 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4091

Abstract: Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss′, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss′.

公开(公告)号：US06404691B1

公开(公告)日：2002-06-11

申请号：US08472770

申请日：1995-06-07

Applicant: Kazuyasu Fujishima ,  Yoshio Matsuda ,  Mikio Asakura

Inventor： Kazuyasu Fujishima ,  Yoshio Matsuda ,  Mikio Asakura

IPC: G11C700

CPC classification number: G06F12/0893 ,  G11C7/1021

Abstract: A semiconductor memory device comprises a DRAM memory cell array comprising a plurality of dynamic type memory cells arranged in a plurality of rows and columns, and an SRAM memory cell array comprising static type memory cells arranged in a plurality of rows and columns. The DRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns. The SRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns, corresponding to the plurality of blocks in the DRAM memory cell array. The SRAM memory cell array is used as a cache memory. At the time of cache hit, data is accessed to the SRAM memory cell array. At the time of cache miss, data is accessed to the DRAM memory cell array. On this occasion, data corresponding to one row in each of the blocks in the DRAM memory cell array is transferred to one row in the corresponding block in the SRAM memory cell array.

Abstract translation: 一种半导体存储器件包括：DRAM存储单元阵列，包括以多行和多列布置的多个动态型存储单元;以及SRAM存储单元阵列，其包括排列成多行和列的静态型存储单元。 DRAM存储单元阵列被分成多个块，每个块包括多个列。 SRAM存储单元阵列被分成多个块，每个块包括对应于DRAM存储单元阵列中的多个块的多个列。 SRAM存储单元阵列用作高速缓冲存储器。 在缓存命中时，数据被访问到SRAM存储单元阵列。 在缓存未命中时，数据被存取到DRAM存储单元阵列。 在这种情况下，对应于DRAM存储单元阵列中的每个块中的一行的数据被传送到SRAM存储单元阵列中相应块中的一行。

公开(公告)号：US6075732A

公开(公告)日：2000-06-13

申请号：US334917

申请日：1999-06-17

Applicant: Tsukasa Ooishi ,  Yoshio Matsuda ,  Kazutami Arimoto ,  Masaki Tsukude ,  Kazuyasu Fujishima

Inventor： Tsukasa Ooishi ,  Yoshio Matsuda ,  Kazutami Arimoto ,  Masaki Tsukude ,  Kazuyasu Fujishima

IPC: G11C11/413 ,  G11C7/00 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L27/10

CPC classification number: G11C29/806 ,  G11C29/781 ,  G11C8/10

Abstract: A semiconductor memory device comprises two memory cell arrays (1a, 1b) in which a block divisional operation is performed. Two spare rows (2a, 2b) are provided corresponding to the two memory cell arrays (1a, 1b). Spare row decoders (5a, 5b) are provided for selecting the spare rows (2a, 2b), respectively. One spare row decoder selecting signal generation circuit (18) used in common by the spare row decoders (5a, 5b) is provided. The spare row decoder selecting signal generation circuit (18) can be previously set so as to generate a spare row decoder selecting signal (SRE) when a defective row exists in either of the memory cell arrays (1a, 1b) and the defective row is selected by row decoder groups (4a, 4b). Each of the spare row decoders (5a, 5b) is activated in response to the spare row decoder selecting signal (SRE) and a block control signal.

Abstract translation: 半导体存储器件包括执行块分割操作的两个存储单元阵列（1a，1b）。 对应于两个存储单元阵列（1a，1b）提供两个备用行（2a，2b）。 备用排解码器​​（5a，5b）分别用于选择备用行（2a，2b）。 提供了由备用行解码器（5a，5b）共同使用的一个备用行解码器选择信号生成电路（18）。 可以预先设置备用行解码器选择信号生成电路（18），以便当在存储单元阵列（1a，1b）中存在缺陷行时产生备用行解码器选择信号（+ E，ovs SRE + EE） ），并且由行解码器组（4a，4b）选择有缺陷的行。 每个备用行解码器（5a，5b）响应于备用行解码器选择信号（+ E，ovs SRE + EE）和块控制信号被激活。

公开(公告)号：USRE36089E

公开(公告)日：1999-02-09

申请号：US652008

申请日：1996-05-23

Applicant: Tsukasa Ooishi ,  Kazutami Arimoto ,  Hideto Hidaka ,  Masanori Hayashikoshi ,  Shinji Kawai ,  Mikio Asakura ,  Masaki Tsukude ,  Katsuhiro Suma ,  Shigeki Tomishima ,  Kazuyasu Fujishima

Inventor： Tsukasa Ooishi ,  Kazutami Arimoto ,  Hideto Hidaka ,  Masanori Hayashikoshi ,  Shinji Kawai ,  Mikio Asakura ,  Masaki Tsukude ,  Katsuhiro Suma ,  Shigeki Tomishima ,  Kazuyasu Fujishima

IPC: G11C11/407 ,  G11C7/10 ,  G11C8/12 ,  G11C11/401 ,  G11C11/41 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC classification number: G11C8/12 ,  G11C7/10

Abstract: Column address A0-A11 is once predecoded by a first predecoder PD1, a second predecoder PD2, and a CDE buffer CDB and then applied to a column decoder CD. Column decoder CD selectively drives one of a plurality of column selecting lines CSL on the basis of the applied predecoded signals. This causes corresponding bit lines in respective memory cell arrays MCA1-MCA4 to be simultaneously selected. Column decoder CD includes a plurality of column drivers corresponding to the plurality of column selecting lines, and the column drivers are divided into a plurality of groups. The predecoded signals applied from second predecoder PD2 and CDE buffer CDB to column decoder CD are generated independently for respective groups, and signal lines for them are also distributed to respective groups. This causes the length of wiring of each predecoded signal line to be shortened.

Abstract translation: 列地址A0-A11由第一预解码器PD1，第二预解码器PD2和CDE缓冲器CDB预先解码，然后应用于列解码器CD。 列解码器CD基于所应用的预解码信号选择性地驱动多个列选择线CSL中的一个。 这使得相应的存储单元阵列MCA1-MCA4中的相应位线被同时选择。 列解码器CD包括对应于多个列选择线的多个列驱动器，列驱动器被分成多个组。 从第二预解码器PD2和CDE缓冲器CDB施加到列解码器CD的预解码信号针对各个组独立地生成，并且它们的信号线也被分配给各个组。 这导致每个预解码信号线的布线长度被缩短。

公开(公告)号：US5504713A

公开(公告)日：1996-04-02

申请号：US180166

申请日：1994-01-11

Applicant: Tsukasa Ooishi ,  Yoshio Matsuda ,  Kazutami Arimoto ,  Masaki Tsukude ,  Kazuyasu Fujishima

Inventor： Tsukasa Ooishi ,  Yoshio Matsuda ,  Kazutami Arimoto ,  Masaki Tsukude ,  Kazuyasu Fujishima

IPC: G11C29/00 ,  G11C7/00

CPC classification number: G11C29/806 ,  G11C29/781

Abstract: A semiconductor memory device comprises two memory cell arrays (1a, 1b) in which a block divisional operation is performed. Two spare rows (2a, 2b) are provided corresponding to the two memory cell arrays (1a, 1b). Spare row decoders (5a, 5b) are provided for selecting the spare rows (2a, 2b), respectively. One spare row decoder selecting signal generation circuit (18) used in common by the spare row decoders (5a, 5b) is provided. The spare row decoder selecting signal generation circuit (18) can be previously set so as to generate a spare row decoder selecting signal (SRE) when a defective row exists in either of the memory cell arrays (1a, 1b) and the defective row is selected by row decoder groups (4a, 4b). Each of the spare row decoders (5a, 5b) is activated in response to the spare row decoder selecting signal (SRE) and a block control signal.

Abstract translation: 半导体存储器件包括执行块分割操作的两个存储单元阵列（1a，1b）。 对应于两个存储单元阵列（1a，1b）提供两个备用行（2a，2b）。 备用排解码器​​（5a，5b）分别用于选择备用行（2a，2b）。 提供了由备用行解码器（5a，5b）共同使用的一个备用行解码器选择信号生成电路（18）。 可以预先设置备用行解码器选择信号生成电路（18），以便当在存储单元阵列（1a，1b）和缺陷行中存在缺陷行时产生备用行解码器选择信号（＆amp; upbar＆S） 由行解码器组（4a，4b）选择。 每个备用行解码器（5a，5b）响应于备用行解码器选择信号（＆amp; S＆amp; S）和块控制信号被激活。

公开(公告)号：US5321657A

公开(公告)日：1994-06-14

申请号：US865145

申请日：1992-04-08

Applicant: Kazutami Arimoto ,  Kazuyasu Fujishima ,  Hideto Hidaka ,  Masaki Tsukude ,  Tsukasa Ohishi

Inventor： Kazutami Arimoto ,  Kazuyasu Fujishima ,  Hideto Hidaka ,  Masaki Tsukude ,  Tsukasa Ohishi

IPC: G11C11/409 ,  G11C7/10 ,  G11C7/12 ,  G11C11/401 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/41 ,  H01L27/10 ,  G11C7/00

CPC classification number: G11C7/12 ,  G11C11/4094 ,  G11C11/4096 ,  G11C7/1048

Abstract: In a dynamic RAM of a CSL system, a memory array is divided into a plurality of memory array portions, and bit line pairs provided in the respective memory array portions are connected to their corresponding I/O line pairs simultaneously in response to a CSL output. In such an RAM, only the I/O line pair of a memory array portion to be accessed is precharged to the level of V.sub.CC -V.sub.th, while the I/O line pair of a memory array portion not to be accessed is precharged to the level of 1/2.multidot.V.sub.CC which is the same level as the bit line pairs. This makes it possible to achieve a faster data reading operation and also prevent unnecessary currents from flowing between the bit line pairs and the I/O line pair in the unaccessed memory array portion.

Abstract translation: 在CSL系统的动态RAM中，存储器阵列被分成多个存储器阵列部分，并且设置在各个存储器阵列部分中的位线对响应于CSL输出而同时连接到它们对应的I / O线对 。 在这样的RAM中，只有要访问的存储器阵列部分的I / O线对被预充电到VCC-Vth的电平，而不存储阵列部分的I / O线对被预充电到 1 / 2xVCC的电平与位线对相同。 这使得可以实现更快的数据读取操作，并且还防止不必要的电流在未加工的存储器阵列部分中的位线对和I / O线对之间流动。

公开(公告)号：US5283762A

公开(公告)日：1994-02-01

申请号：US695028

申请日：1991-05-06

Applicant: Kazuyasu Fujishima

Inventor： Kazuyasu Fujishima

IPC: G05F1/46 ,  G05F3/24 ,  G11C5/14 ,  H03F3/45 ,  G11C13/00

CPC classification number: G05F1/465 ,  G05F3/24 ,  G11C5/147 ,  H03F3/45076 ,  Y10T307/62

Abstract: The semiconductor memory device contains a voltage converting circuit. The voltage converting circuit includes a plurality of reference voltage generating circuits for respectively generating a plurality of reference voltages at different levels. The voltage converting circuit further includes a differential amplifier, an output circuit, a switching circuit and a switching control circuit. The switching control circuit and the switching circuit select one of the plurality of reference voltages and supply the selected reference voltage to the differential amplifier in response to an externally applied control signal. The differential amplifier and the output circuit apply the supplied reference voltage to an internal circuit.

Abstract translation: 半导体存储器件包含电压转换电路。 电压转换电路包括用于分别产生不同电平的多个参考电压的多个参考电压发生电路。 电压转换电路还包括差分放大器，输出电路，开关电路和开关控制电路。 开关控制电路和开关电路选择多个参考电压之一并响应于外部施加的控制信号将所选择的参考电压提供给差分放大器。 差分放大器和输出电路将提供的参考电压施加到内部电路。