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    Semiconductor memory device including memory cell transistors formed on SOI substrate and having fixed body regions
    5.
    发明授权
    Semiconductor memory device including memory cell transistors formed on SOI substrate and having fixed body regions 失效

    公开(公告)号：US6018172A

    公开(公告)日：2000-01-25

    申请号：US501525

    申请日：1995-07-12

    Applicant: Hideto Hidaka ,  Takahiro Tsuruda ,  Katsuhiro Suma

    Inventor： Hideto Hidaka ,  Takahiro Tsuruda ,  Katsuhiro Suma

    IPC: G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  H01L21/8242 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786

    CPC classification number: H01L27/10882 ,  H01L27/10897 ,  H01L27/1203 ,  H01L27/10808

    Abstract: A semiconductor memory device includes an SOI substrate, a plurality of word lines, a plurality of bit line pairs, a plurality of memory cells and a plurality of body fixing lines. The plurality of word lines are disposed in the row direction on the SOI substrate. The plurality of bit line pairs are disposed in the column direction on the SOI substrate. The plurality of memory cells are located on the SOI substrate and each are disposed correspondingly to one of crossings between the plurality of word lines and the plurality of bit line pairs. Each of the plurality of memory cells includes a capacitor and a transistor. The transistor is connected between the capacitor and one bit line in the corresponding bit line pair. The transistor is turned on in response to the potential of the corresponding word line. The plurality of body fixing lines are disposed on the SOI substrate. The plurality of body fixing lines are supplied with a predetermined potential. The transistors in the plurality of memory cells have source regions, drain regions and body regions located between the source and drain regions. The body regions of the transistors in the plurality of memory cells are connected to the plurality of body fixing lines.

    Arrangement enabling pin contact test of a semiconductor device having clamp protection circuit, and method of testing a semiconductor device
    6.
    发明授权
    Arrangement enabling pin contact test of a semiconductor device having clamp protection circuit, and method of testing a semiconductor device 失效
    具有钳位保护电路的半导体器件的针接触测试的布置以及半导体器件的测试方法

    公开(公告)号：US5770964A

    公开(公告)日：1998-06-23

    申请号：US675759

    申请日：1996-07-03

    Applicant: Katsuhiro Suma

    Inventor： Katsuhiro Suma

    IPC: G01R31/26 ,  G01R31/28 ,  G01R31/3185 ,  G11C29/00 ,  G11C29/56 ,  H03K5/08

    CPC classification number: G11C29/022 ,  G01R31/3185 ,  H03K5/08

    Abstract: A clamp circuit for clamping potential of an internal node electrically connected to an external terminal has its clamping function activated and inactivated selectively in accordance with a control signal generated by a control circuit in response to a forced monitor mode activating signal. An output portion of a substrate potential generating circuit generating a prescribed internal voltage is selectively connected to the internal node in response to a control signal generated from a second control circuit in response to the forced monitor mode activating signal. In a semiconductor device having the clamp circuit for absorbing surge current, pin contact test, external monitoring of an internal potential and external application of the internal potential can be realized.

    Abstract translation: 用于钳位电连接到外部端子的内部节点的电位，其钳位功能根据由控制电路响应于强制监视模式激活信号而产生的控制信号选择性地激活和失活。 响应于从第二控制电路产生的响应于强制监视模式激活信号的控制信号，产生规定内部电压的衬底电位产生电路的输出部分选择性地连接到内部节点。 在具有用于吸收浪涌电流的钳位电路的半导体器件中，可以实现针接触测试，内部电位的外部监测和内部电位的外部应用。

    Semiconductor memory device including an SOI substrate
    7.
    发明授权
    Semiconductor memory device including an SOI substrate 失效
    包括SOI衬底的半导体存储器件

    公开(公告)号：US07242060B2

    公开(公告)日：2007-07-10

    申请号：US11333351

    申请日：2006-01-18

    Applicant: Hideto Hidaka ,  Katsuhiro Suma ,  Takahiro Tsuruda

    Inventor： Hideto Hidaka ,  Katsuhiro Suma ,  Takahiro Tsuruda

    IPC: H01L27/01

    CPC classification number: H01L27/10897 ,  G11C11/404 ,  G11C11/4097 ,  G11C2211/4016 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/1203

    Abstract: A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.

    Abstract translation: 半导体存储器件包括多个N沟道MOS晶体管和P沟道MOS晶体管。 多个MOS晶体管形成在SOI（绝缘体上硅）衬底上。 每个MOS晶体管包括源极区域，漏极区域和位于源极区域和漏极区域之间的体区域。 至少一个N沟道MOS晶体管的体区电气固定。 至少一个P沟道MOS晶体管的体区被浮置。

    Semiconductor device using an SOI substrate
    9.
    发明授权
    Semiconductor device using an SOI substrate 失效
    使用SOI衬底的半导体器件

    公开(公告)号：US06586803B2

    公开(公告)日：2003-07-01

    申请号：US09370220

    申请日：1999-08-09

    Applicant: Hideto Hidaka ,  Katsuhiro Suma ,  Takahiro Tsuruda

    Inventor： Hideto Hidaka ,  Katsuhiro Suma ,  Takahiro Tsuruda

    IPC: H01L2701

    CPC classification number: H01L27/1203

    Abstract: A semiconductor device includes an SOI substrate, trench memory cells including trench capacitors formed in the SOI substrate and a mesa or trench isolation region for isolating the trench memory cells. As a result, the trench memory cells are isolated more completely and soft errors are reduced.

    Abstract translation: 半导体器件包括SOI衬底，包括形成在SOI衬底中的沟槽电容器的沟槽存储器单元和用于隔离沟槽存储器单元的台面或沟槽隔离区域。 结果，沟槽存储器单元被更完全隔离，并且软错误被减少。

    Semiconductor memory device including an SOI substrate
    10.
    发明授权
    Semiconductor memory device including an SOI substrate 失效
    包括SOI衬底的半导体存储器件

    公开(公告)号：US06385159B2

    公开(公告)日：2002-05-07

    申请号：US09816402

    申请日：2001-03-26

    Applicant: Hideto Hidaka ,  Katsuhiro Suma ,  Takahiro Tsuruda

    Inventor： Hideto Hidaka ,  Katsuhiro Suma ,  Takahiro Tsuruda

    IPC: G11C1140

    CPC classification number: H01L27/10897 ,  G11C11/404 ,  G11C11/4097 ,  G11C2211/4016 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/1203

    Abstract: A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.

    Abstract translation: 半导体存储器件包括多个N沟道MOS晶体管和P沟道MOS晶体管。 多个MOS晶体管形成在SOI（绝缘体上硅）衬底上。 每个MOS晶体管包括源极区域，漏极区域和位于源极区域和漏极区域之间的体区域。 至少一个N沟道MOS晶体管的体区电气固定。 至少一个P沟道MOS晶体管的体区被浮置。

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