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94 条记录 (耗时 0.018 秒)

    Flash memory array using adjacent bit line as source
    73.
    发明申请
    Flash memory array using adjacent bit line as source 有权

    公开(公告)号：US20060256618A1

    公开(公告)日：2006-11-16

    申请号：US11127466

    申请日：2005-05-12

    申请人： Hagop Nazarian

    发明人： Hagop Nazarian

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483 ,  G11C16/0491

    摘要： A memory array having a plurality of flash memory cells arranged in rows and columns. A plurality of bit lines couple the columns such that alternate bit lines of the plurality of bit lines are adapted to operate as either source lines or bit lines in response to bit line selection and biasing.

    Voltage booster
    74.
    发明申请
    Voltage booster 失效

    公开(公告)号：US20050219902A1

    公开(公告)日：2005-10-06

    申请号：US11137941

    申请日：2005-05-26

    申请人： Hagop Nazarian ,  Dzung Nguyen

    发明人： Hagop Nazarian ,  Dzung Nguyen

    IPC分类号： G05F1/10 ,  G11C5/14 ,  G11C11/34 ,  G11C16/08 ,  G11C16/30 ,  H02M3/07

    CPC分类号： G11C5/145 ,  G11C16/08 ,  G11C16/30 ,  H02M3/073

    摘要： Voltage boosters or pass circuits for generating a boosted voltage are advantageous in the decoding and programming of memory devices and, in particular, NAND flash memory devices. The boosted voltage can be used as a gate voltage for a pass gate providing programming voltages to a selected block of memory cells, such as in a NAND flash memory array. The pass circuits facilitate the elimination of high-voltage p-channel devices by providing a boosted voltage using n-channel devices. The pass circuits further permit control of multiple pass gates using a single boosted voltage source.

    Voltage booster
    75.
    发明申请
    Voltage booster 有权

    公开(公告)号：US20050093613A1

    公开(公告)日：2005-05-05

    申请号：US10701141

    申请日：2003-11-04

    申请人： Hagop Nazarian ,  Dzung Nguyen

    发明人： Hagop Nazarian ,  Dzung Nguyen

    IPC分类号： G05F1/10 ,  G11C5/14 ,  G11C11/34 ,  G11C16/08 ,  G11C16/30 ,  H02M3/07

    CPC分类号： G11C5/145 ,  G11C16/08 ,  G11C16/30 ,  H02M3/073

    摘要： Voltage boosters or pass circuits for generating a boosted voltage are advantageous in the decoding and programming of memory devices and, in particular, NAND flash memory devices. The boosted voltage can be used as a gate voltage for a pass gate providing programming voltages to a selected block of memory cells, such as in a NAND flash memory array. The pass circuits facilitate the elimination of high-voltage p-channel devices by providing a boosted voltage using n-channel devices. The pass circuits further permit control of multiple pass gates using a single boosted voltage source.

    High speed configuration independent programmable macrocell
    76.
    发明授权
    High speed configuration independent programmable macrocell 失效
    高速配置独立的可编程宏单元

    公开(公告)号：US5502403A

    公开(公告)日：1996-03-26

    申请号：US360469

    申请日：1994-12-20

    申请人： Lin-Shih Liu ,  Syed B. Raza ,  Hagop Nazarian ,  George M. Ansel ,  Stephen M. Douglass ,  Jeffery S. Hunt

    发明人： Lin-Shih Liu ,  Syed B. Raza ,  Hagop Nazarian ,  George M. Ansel ,  Stephen M. Douglass ,  Jeffery S. Hunt

    IPC分类号： H03K19/173 ,  H03K19/0948

    CPC分类号： H03K19/1736

    摘要： A user configurable circuit contains clock logic, a switching element and a data path circuit. Input data is received in the switching element, and the switching element and the data path circuit constitute the entire data path for the circuit. A plurality of user configurable inputs are received to configure the circuit for a particular user application. The clock logic and the switching element implement a logic function that is configurable by the user configurable inputs. The logic function is pre-processed in the clock logic so that minimal delay occurs in the data path. In addition, the propagation delay through the switching element and the register is independent of the user configurable inputs. The user configurable circuit of the present invention has application for use as a macro cell for a programmable logic device permitting the user to configure the circuit as a D-type flip-flop, a T-type flip-flop. In addition, the user selects the polarity for the output circuit.

    摘要翻译： 用户可配置电路包含时钟逻辑，开关元件和数据路径电路。 在开关元件中接收输入数据，并且开关元件和数据路径电路构成电路的整个数据路径。 接收多个用户可配置输入以为特定用户应用配置电路。 时钟逻辑和开关元件实现可由用户可配置输入配置的逻辑功能。 逻辑功能在时钟逻辑中被预处理，从而在数据通路中发生最小的延迟。 此外，通过开关元件和寄存器的传播延迟与用户可配置输入无关。 本发明的用户可配置电路具有用作可编程逻辑器件的宏小区的应用，允许用户将电路配置为D型触发器，T型触发器。 此外，用户选择输出电路的极性。

    Disturb-resistant non-volatile memory device and method
    78.
    发明授权
    Disturb-resistant non-volatile memory device and method 有权
    抗干扰的非易失性存储器件及方法

    公开(公告)号：US08404553B2

    公开(公告)日：2013-03-26

    申请号：US12861666

    申请日：2010-08-23

    申请人： Scott Brad Herner ,  Hagop Nazarian

    发明人： Scott Brad Herner ,  Hagop Nazarian

    IPC分类号： H01L21/20

    CPC分类号： H01L27/2463 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/1253 ,  H01L45/14 ,  H01L45/148 ,  H01L45/1608 ,  H01L45/1675

    摘要： A method of forming a disturb-resistant non volatile memory device. The method includes providing a semiconductor substrate having a surface region and forming a first dielectric material overlying the surface region. A first wiring material overlies the first dielectric material, a doped polysilicon material overlies the first wiring material, and an amorphous silicon switching material overlies the said polysilicon material. The switching material is subjected to a first patterning and etching process to separating a first strip of switching material from a second strip of switching spatially oriented in a first direction. The first strip of switching material, the second strip of switching material, the contact material, and the first wiring material are subjected to a second patterning and etching process to form at least a first switching element from the first strip of switching material and at least a second switching element from the second strip of switching material, and a first wiring structure comprising at least the first wiring material and the contact material. The first wiring structure being is in a second direction at an angle to the first direction.

    摘要翻译： 一种形成抗干扰非易失性存储器件的方法。 该方法包括提供具有表面区域并形成覆盖表面区域的第一电介质材料的半导体衬底。 第一布线材料覆盖在第一介电材料上，掺杂多晶硅材料覆盖在第一布线材料上，非晶硅开关材料覆盖在所述多晶硅材料上。 对开关材料进行第一图案化和蚀刻工艺，以将第一条开关材料与在第一方向上空间取向的第二开关条分离。 第一切换材料条，第二条切换材料，接触材料和第一布线材料经受第二图案化和蚀刻工艺，以从第一条开关材料形成至少第一开关元件，并且至少 来自所述第二开关材料条的第二开关元件，以及至少包括所述第一布线材料和所述接触材料的第一布线结构。 第一布线结构处于与第一方向成一定角度的第二方向。

    Error correction for flash memory
    80.
    发明授权
    Error correction for flash memory 有权
    闪存的错误更正

    公开(公告)号：US08296626B2

    公开(公告)日：2012-10-23

    申请号：US12267017

    申请日：2008-11-07

    申请人： Hagop Nazarian ,  Ping Hou

    发明人： Hagop Nazarian ,  Ping Hou

    IPC分类号： G11C29/00

    CPC分类号： G06F11/1072 ,  G11C2029/0411

    摘要： Providing for single and multi-bit error correction of electronic memory is described herein. As an example, error correction can be accomplished by establishing a suspect region between bit level distributions of a set of analyzed memory cells. The suspect region can define potential error bits for the distributions. If a bit error is detected for the distributions, error correction can first be applied to the potential error bits in the suspect region. By identifying suspected error bits and limiting initial error correction to such identified bits, complexities involved in applying error correction to all bits of the distributions can be mitigated or avoided, improving efficiency of bit error corrections for electronic memory.

    摘要翻译： 本文描述了提供电子存储器的单位和多位纠错。 作为示例，可以通过在一组分析的存储器单元的位级分布之间建立可疑区域来实现纠错。 可疑区域可以定义分布的潜在错误位。 如果对于分布检测到位错误，则可以首先将错误校正应用于可疑区域中的潜在错误位。 通过识别怀疑的错误位并将初始误差修正限制在这种识别的位上，可以减轻或避免对分布的所有位应用纠错所涉及的复杂性，从而提高电子存储器误码校正的效率。