公开(公告)号：US12066890B2

公开(公告)日：2024-08-20

申请号：US17704474

申请日：2022-03-25

申请人： Advanced Micro Devices, Inc.

发明人： Sudhanva Gurumurthi ,  Ganesh Suryanarayan Dasika

IPC分类号： G11C29/00 ,  G06F11/07 ,  G06F11/10 ,  G06N20/00

CPC分类号： G06F11/1068 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/1004 ,  G06N20/00

摘要： A memory system uses error detection codes to detect when errors have occurred in a region of memory. A count of the number of errors is kept and a notification is output in response to the number of errors satisfying a threshold value. The notification is an indication to a host (e.g., a program accessing or managing a machine learning system) that the threshold number of errors have been detected in the region of memory. As long as the number of errors that have been detected in the region of memory remains under the threshold number no notification need be output to the host.

公开(公告)号：US12066889B2

公开(公告)日：2024-08-20

申请号：US17239621

申请日：2021-04-25

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Kicheol Eom ,  Jaeho Sim ,  Dong-Ryoul Lee ,  Hyun Ju Yi ,  Hyotaek Leem

IPC分类号： G06F11/10 ,  G06F3/06 ,  G06F13/16 ,  G06F13/28 ,  G06F13/42

CPC分类号： G06F11/1068 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F13/1668 ,  G06F13/28 ,  G06F13/4282

摘要： A storage device sharing a host memory of a host, the storage device includes a serial interface that exchanges data with the host, and a storage controller that stores buffering data in a host memory buffer allocated by the host through the serial interface. The storage controller performs error correction encoding and error correction decoding on the buffering data.

公开(公告)号：US20240272987A1

公开(公告)日：2024-08-15

申请号：US18166733

申请日：2023-02-09

申请人： International Business Machines Corporation

发明人： Lee Jason Sanders ,  Ben Sasson ,  Roderick Guy Charles Moore ,  Paul Nicholas Cashman

IPC分类号： G06F11/14 ,  G06F11/10

CPC分类号： G06F11/1435 ,  G06F11/1016

摘要： A computer-implemented method for detecting data storage errors includes storing first data in a first block corresponding to a first virtual volume, storing second data in a second block corresponding to a second virtual volume, generating parity information for the first data and the second data, and storing the parity information in non-volatile memory at a location corresponding to the logical block address to produce stored parity information. A system and computer program product corresponding to the above method are also disclosed herein.

公开(公告)号：US12061518B2

公开(公告)日：2024-08-13

申请号：US18108876

申请日：2023-02-13

申请人： Micron Technology, Inc.

发明人： Sai Krishna Mylavarapu ,  Todd A. Marquart

IPC分类号： G06F11/10 ,  G11C11/00 ,  G11C11/4074 ,  G11C11/4096

CPC分类号： G06F11/1004 ,  G06F11/1068 ,  G11C11/005 ,  G11C11/4074 ,  G11C11/4096

摘要： Methods, devices, and systems related to storing parity data in dynamic random access memory (DRAM) are described. In an example, a method can include generating, at a controller, parity data based on user data queued for writing to a non-volatile memory device, receiving the parity data at a DRAM device from the controller and writing the parity data to the DRAM device, receiving the user data at a non-volatile memory device from the controller and writing the user data to the non-volatile memory device, reading the user data from the non-volatile memory device via the controller, and receiving the parity data at the controller from the DRAM device.

公开(公告)号：US20240264952A1

公开(公告)日：2024-08-08

申请号：US18639013

申请日：2024-04-18

申请人： Texas Instruments Incorporated

发明人： Naveen BHORIA ,  Timothy David ANDERSON ,  Pete HIPPLEHEUSER

IPC分类号： G06F12/128 ,  G06F9/30 ,  G06F9/54 ,  G06F11/10 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0853 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/12 ,  G06F12/121 ,  G06F12/126 ,  G06F12/127 ,  G06F13/16 ,  G06F15/80 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C29/42 ,  G11C29/44

CPC分类号： G06F12/128 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/546 ,  G06F11/1064 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0292 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/082 ,  G06F12/0853 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/12 ,  G06F12/121 ,  G06F12/126 ,  G06F12/127 ,  G06F13/1605 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/1689 ,  G06F15/8069 ,  G11C5/066 ,  G11C7/10 ,  G11C7/1015 ,  G11C7/106 ,  G11C7/1075 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/222 ,  G11C29/42 ,  G11C29/44 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/1041 ,  G06F2212/1044 ,  G06F2212/301 ,  G06F2212/454 ,  G06F2212/603 ,  G06F2212/6032 ,  G06F2212/6042 ,  G06F2212/608 ,  G06F2212/62

摘要： A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes a set of cache lines, line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and an eviction controller configured to flush stored write-miss data based on the line type bits.

公开(公告)号：US12056007B2

公开(公告)日：2024-08-06

申请号：US17702291

申请日：2022-03-23

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Eun Chu Oh ,  Junyeong Seok ,  Younggul Song ,  Byungchul Jang

IPC分类号： G06F11/10 ,  G06F11/07 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096

CPC分类号： G06F11/1068 ,  G06F11/076 ,  G11C11/4074 ,  G11C11/4082 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/4096

摘要： A storage device includes a NAND flash memory device, an auxiliary memory device and a storage controller to control the NAND flash memory device and the auxiliary memory device. The storage controller includes a processor, an error correction code (ECC) engine and a memory interface. The processor executes a flash translation layer (FTL) loaded onto an on-chip memory. The ECC engine generates first parity bits for user data to be stored in a target page of the NAND flash memory device based on error attribute of a target memory region associated with the target page, and selectively generates additional parity bits for the user data under control of the processor. The memory interface transmits the user data and the first parity bits to the NAND flash memory device, and selectively transmits the additional parity bits to the auxiliary memory device.

公开(公告)号：US12050515B2

公开(公告)日：2024-07-30

申请号：US18194511

申请日：2023-03-31

申请人： SK hynix Inc.

发明人： Jin Ho Baek ,  Young Pyo Joo

IPC分类号： G11C29/00 ,  G06F11/07 ,  G06F11/10

CPC分类号： G06F11/1068 ,  G06F11/076

摘要： A computing system comprises a memory and a controller, and the controller is configured to store a first type of data and a second type of data in the memory, to divide the first type of data into a first part and a second part, to generate parity information on the first part and to store the parity information in the memory, and a refresh interval of a region of the memory where the first type of data is stored is larger than a refresh interval of a region of the memory where the second type of data is stored.

公开(公告)号：US12050514B1

公开(公告)日：2024-07-30

申请号：US18184872

申请日：2023-03-16

申请人： Kioxia Corporation

发明人： Avi Steiner ,  Ofir Kanter

IPC分类号： G06F11/10 ,  H03M13/15

CPC分类号： G06F11/1068 ,  H03M13/152

摘要： Systems, methods, non-transitory computer-readable media to perform operations associated with the storage medium. One system includes a storage medium and an encoding/decoding (ED) system to perform operations associated with the storage medium, the ED system being configured to process a set of log-likelihood ratios (LLRs) and a syndrome vector to obtain a set of confidence values for each bit of a codeword, estimate an error vector based on selecting one or more bit locations with confidence values from the set of confidence values above threshold value and applying hard decision decoding to the selected one or more bit locations, calculate a sum LLR score for the estimated error vector, and output a decoded codeword based on the estimated error vector and the sum LLR score.

公开(公告)号：US20240248796A1

公开(公告)日：2024-07-25

申请号：US18625539

申请日：2024-04-03

申请人： Micron Technology, Inc.

发明人： Sujeet Ayyapureddi

IPC分类号： G06F11/10

CPC分类号： G06F11/106

摘要： Apparatuses, systems, and methods for per row error correct and scrub (pRECS) information. There may be pRECS information associated with each row, and it may reflect a number of codewords stored along that row which were determined to include an error during error correct and scrub (ECS) operations. The memory may store the pRECS information in the memory array, for example, each row may store the pRECS information associated with that row.

公开(公告)号：US20240248632A1

公开(公告)日：2024-07-25

申请号：US18444870

申请日：2024-02-19

申请人： Pure Storage, Inc.

发明人： Bart R. Cilfone ,  Patrick A. Tamborski

IPC分类号： G06F3/06 ,  G06F8/65 ,  G06F11/10 ,  H03M13/15 ,  H03M13/37 ,  H04L9/40 ,  H04L67/00 ,  H04L67/01 ,  H04L67/02 ,  H04L67/06 ,  H04L67/1097 ,  H04L67/60

CPC分类号： G06F3/0653 ,  G06F3/0611 ,  G06F3/0614 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0661 ,  G06F3/067 ,  G06F8/65 ,  G06F11/1092 ,  H03M13/154 ,  H03M13/3761 ,  H04L63/061 ,  H04L67/1097 ,  H04L67/34 ,  H04L67/60 ,  H03M13/1515 ,  H04L67/01 ,  H04L67/02 ,  H04L67/06

摘要： Apparatus and methods for use in coordinating distributed computing networks such as distributed storage networks. In an embodiment, a coordination unit establishes connections with managing units of the distributed computing networks. For example, the managing units can initiate the connections via connection messages. The coordination unit further transmits coordination messages to the managing units. The coordination messages can include update information and requests specifying information gathering tasks to be executed by the distributed computing networks. In an example, the coordination unit receives a response to a first coordination message from a first managing unit. The coordination unit transmits a second coordination message to a second managing unit, wherein the second coordination message includes information related to the information gathered by the first distributed computing network in response to the first coordination message.