公开(公告)号：US20240215460A1

公开(公告)日：2024-06-27

申请号：US18069996

申请日：2022-12-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Baleegh Abdo ,  Jae-Woong Nah

IPC: H10N60/81 ,  H10N60/01 ,  H10N60/82 ,  H10N69/00

CPC classification number: H10N60/81 ,  H10N60/01 ,  H10N60/82 ,  H10N69/00

Abstract: A structure includes a first device having a first chip and a second chip. The second chip has a first side with a plurality of bumps and a second side with a plurality of first superconducting lines. A solder bonded layer attaches the first chip to the second chip. A second device has a first side with a plurality of pads facing the plurality of bumps in the second chip and a second side opposite the first side having a plurality of second superconducting lines. A solder shield material surrounds the plurality of bumps and the plurality of pads, and the plurality of bumps on the second chip are bonded to the plurality of pads on the second device. The solder shield material is connected to the plurality of first superconducting lines of the first device and to the plurality of second superconducting lines of the second device.

公开(公告)号：US12004286B2

公开(公告)日：2024-06-04

申请号：US17898065

申请日：2022-08-29

Applicant: FERMI RESEARCH ALLIANCE, LLC

Inventor： Alexander Romanenko ,  Sam Posen ,  Anna Grassellino

IPC: H05H7/20 ,  G06N10/00 ,  H01P7/06 ,  H10N60/01

CPC classification number: H05H7/20 ,  G06N10/00 ,  H01P7/06 ,  H10N60/01

Abstract: A system and method for treating a cavity comprises preparing a superconducting radio frequency (SRF) cavity for removal of a dielectric layer from on an inner surface of the SRF cavity, subjecting the SRF cavity to a heat treatment in order to remove the dielectric layer from the inner surface of the SRF cavity, and preventing the development of a new dielectric layer on the inner surface of the SRF cavity by preventing an interaction between the inner surface of the SRF cavity and atmospheric gasses.

公开(公告)号：US20240177927A1

公开(公告)日：2024-05-30

申请号：US18433052

申请日：2024-02-05

Applicant: Richard Thuss ,  Lawrence Livermore National Security, LLC

Inventor： Alexander Baker ,  Scott K. McCall ,  Harry B. Radousky ,  Nathan Woollett ,  Richard Thuss

IPC: H01F41/14 ,  B22F10/25 ,  B22F10/38 ,  B32B1/00 ,  B32B3/02 ,  B32B3/26 ,  B32B3/30 ,  B32B5/14 ,  B32B5/16 ,  B32B7/025 ,  B32B7/027 ,  B32B15/04 ,  B33Y80/00 ,  C23C4/01 ,  C23C4/04 ,  C23C4/06 ,  C23C4/08 ,  C23C4/12 ,  C23C24/00 ,  C23C24/04 ,  C23C30/00 ,  H01F7/00 ,  H01F7/02 ,  H01F41/20 ,  H01F41/30 ,  H01F41/34 ,  H10N10/00 ,  H10N10/80 ,  H10N10/857 ,  H10N15/00 ,  H10N30/00 ,  H10N30/01 ,  H10N30/074 ,  H10N30/076 ,  H10N60/00 ,  H10N60/01 ,  B33Y10/00 ,  H10N10/01

CPC classification number: H01F41/14 ,  B22F10/25 ,  B22F10/38 ,  B32B1/00 ,  B32B3/02 ,  B32B3/26 ,  B32B3/30 ,  B32B5/14 ,  B32B5/142 ,  B32B5/145 ,  B32B5/16 ,  B32B7/025 ,  B32B7/027 ,  B32B15/04 ,  B32B15/043 ,  B33Y80/00 ,  C23C4/01 ,  C23C4/04 ,  C23C4/06 ,  C23C4/08 ,  C23C4/12 ,  C23C24/00 ,  C23C24/04 ,  C23C30/00 ,  C23C30/005 ,  H01F7/00 ,  H01F7/02 ,  H01F41/20 ,  H01F41/30 ,  H01F41/34 ,  H10N10/00 ,  H10N10/80 ,  H10N10/857 ,  H10N15/00 ,  H10N30/00 ,  H10N30/01 ,  H10N30/074 ,  H10N30/076 ,  H10N30/1051 ,  H10N60/00 ,  H10N60/01 ,  B22F2999/00 ,  B33Y10/00 ,  C22C2202/00 ,  H10N10/01 ,  Y10T428/12389 ,  Y10T428/12396 ,  Y10T428/12458 ,  Y10T428/12493 ,  Y10T428/12528 ,  Y10T428/12535 ,  Y10T428/12681 ,  Y10T428/24942 ,  Y10T428/249921 ,  Y10T428/26

Abstract: A method, in accordance with one embodiment, includes forming an array of structures from a raw material via cold spray. Each of the structures is characterized by having a defined feature size in at least one dimension of less than 100 microns as measured in a plane of deposition of the structure, at least 90% of a theoretical density of the raw material, and essentially the same functional properties as the raw material. A method, in accordance with another embodiment, includes positioning a mask between a cold spray nozzle and a substrate, and forming a structure on the substrate by cold spraying a raw material from the cold spray nozzle. The structure has a shape corresponding to an aperture in the mask.

公开(公告)号：US20240164221A1

公开(公告)日：2024-05-16

申请号：US18486548

申请日：2023-10-13

Applicant: Alibaba Damo (Hangzhou) Technology Co., Ltd.

Inventor： Hao DENG ,  Xiaohang ZHANG

IPC: H10N60/01 ,  G06N10/40 ,  H10N60/85

CPC classification number: H10N60/01 ,  G06N10/40 ,  H10N60/85

Abstract: The present disclosure discloses a method for treating a tantalum metal thin film, a quantum device, and a quantum chip. The method includes: preparing an initial tantalum metal thin film; and increasing, after cooling the initial tantalum metal thin film to a predetermined extremely low temperature, the temperature from the predetermined extremely low temperature to normal temperature to obtain a target tantalum metal thin film. The present disclosure solves the technical problem in the related technology: a post-treatment technology for a tantalum metal thin film after preparation of the tantalum metal thin film has a limited positive effect on reducing the energy dissipation of a tantalum-based superconducting quantum device.

公开(公告)号：US20240107897A1

公开(公告)日：2024-03-28

申请号：US17753581

申请日：2019-09-10

Applicant: Microsoft Technology Licensing, LLC

Inventor： Pavel ASEEV ,  Philippe CAROFF-GAONAC'H ,  Leonardus Petrus KOUWENHOVEN

IPC: H10N60/01 ,  C30B25/04 ,  C30B29/40 ,  C30B29/60 ,  H10N69/00

CPC classification number: H10N60/01 ,  C30B25/04 ,  C30B29/40 ,  C30B29/60 ,  H10N69/00

Abstract: A fabrication method comprising: forming a mask of an amorphous material over a crystalline surface of a substrate, the mask having a pattern of openings defining areas of an active region in which one or more components of one or more active devices are to be formed, the mask further defining a non-active region in which no active devices are to be formed; and forming a deposition material through the mask by an epitaxial growth process. The deposition material thus forms in the openings of the active region. The pattern of openings through the mask further comprises one or more reservoirs formed in the non-active region, each of the reservoirs being connected by the pattern of openings in the mask to at least one of the areas in the active region, and the deposition material forming in the reservoirs as part of the epitaxial growth.

公开(公告)号：US20240074331A1

公开(公告)日：2024-02-29

申请号：US18261102

申请日：2021-01-13

Applicant: Microsoft Technology Licensing, LLC

Inventor： Esteban Adrian MARTINEZ ,  Saulius VAITIEKENAS ,  Lucas CASPARIS ,  Esben Bork HANSEN

IPC: H10N60/10 ,  G01R19/00 ,  H10N60/01

CPC classification number: H10N60/128 ,  G01R19/0092 ,  H10N60/01

Abstract: A semiconductor-superconductor hybrid device comprises a semiconductor component having first and second terminals, first and second gate electrodes for electrostatically gating the first and second terminals. A second gate electrode electrostatically gates the second terminal, and a superconductor component is configured for energy level hybridisation with the semiconductor component. A method of measuring a non-local conductance of the semiconductor component comprises applying a first gate voltage to the first gate electrode to gate the first terminal to an open regime, applying a second gate voltage to the second gate electrode to gate the second terminal to a tunnelling regime, applying a bias voltage to the first terminal, and while applying the first gate voltage, the second gate voltage, and the bias voltage, measuring a current through the second terminal; with the superconductor component grounded.

公开(公告)号：US20240062933A1

公开(公告)日：2024-02-22

申请号：US17945351

申请日：2022-09-15

Applicant: Ambature, Inc.

Inventor： Douglas J. Gilbert ,  Timothy S. Cale

IPC: H01B12/06 ,  H01B1/08 ,  H01C7/00 ,  H10N60/01 ,  H10N60/85 ,  B05D1/36 ,  H01B12/14

CPC classification number: H01B12/06 ,  H01B1/08 ,  H01C7/00 ,  H10N60/01 ,  H10N60/85 ,  H10N60/0268 ,  H10N60/855 ,  H10N60/0856 ,  H10N60/857 ,  B05D1/36 ,  H01B12/14 ,  Y10T428/31678 ,  H10N60/0661

Abstract: Operational characteristics of an extremely low resistance (“ELR”) film comprised of an ELR material may be improved by depositing a modifying material onto appropriate surfaces of the ELR film to create a modified ELR film. In some implementations of the invention, the ELR film may be in the form of a “c-film.” In some implementations of the invention, the ELR film may be in the form of an “a-b film,” an “a-film” or a “b-film.” The modified ELR film has improved operational characteristics over the ELR film alone or without the modifying material. Such operational characteristics may include operating in an ELR state at increased temperatures, carrying additional electrical charge, operating with improved magnetic properties, operating with improved mechanic properties or other improved operational characteristics. In some implementations of the invention, the ELR material is a mixed-valence copper-oxide perovskite, such as, but not limited to YBCO. In some implementations of the invention, the modifying material is a conductive material that bonds easily to oxygen, such as, but not limited to, chromium.

公开(公告)号：US11903330B2

公开(公告)日：2024-02-13

申请号：US17378375

申请日：2021-07-16

Applicant: NEW YORK UNIVERSITY

Inventor： Javad Shabani ,  Matthieu C. Dartiailh

IPC: H10N60/12 ,  G06N10/40 ,  H10N60/01 ,  H10N60/10

CPC classification number: H10N60/12 ,  G06N10/40 ,  H10N60/01 ,  H10N60/0912 ,  H10N60/128

Abstract: The method of performing braiding operations can include providing a first Josephson junction including first gates. The method can include providing a second Josephson junction including second gates. The method can include tuning the first gates to dispose a first pair of Majorana fermions a first region. The method can include tuning the second gates to dispose a second pair of Majorana fermions in a second region. The method can include tuning the first gates to dispose a first Majorana fermion in the first region and to dispose a second Majorana fermion in a third region. The method can include tuning the second gates to dispose a third Majorana fermion in a fourth region and to dispose a fourth Majorana fermion in the second region.

公开(公告)号：US11894162B2

公开(公告)日：2024-02-06

申请号：US17917669

申请日：2021-02-11

Applicant: University of Pittsburgh—Of the Commonwealth System of Higher Education

Inventor： Jeremy Levy

IPC: G21K5/04 ,  H10N60/01 ,  H10N70/20 ,  H10N52/01 ,  H10N60/30 ,  H10N70/00 ,  H01J37/147 ,  H01J37/28 ,  H01J37/317

CPC classification number: G21K5/04 ,  H01J37/147 ,  H01J37/28 ,  H01J37/3174 ,  H10N52/01 ,  H10N60/01 ,  H10N60/30 ,  H10N70/041 ,  H10N70/257 ,  H01J2237/004

Abstract: Described is a method comprising directing an ultra-low voltage electron beam to a surface of a first insulating layer. The first insulating layer is disposed on a second insulating layer. The method includes modifying, by the application of the ultra-low voltage electron beam, the surface of the first insulating layer to selectively switch an interface between a first state having a first electronic property and a second state having a second electronic property.

公开(公告)号：US11849651B2

公开(公告)日：2023-12-19

申请号：US17576538

申请日：2022-01-14

Applicant: IQM Finland Oy

Inventor： Tianyi Li ,  Wei Liu ,  Manjunath Ramachandrappa Venkatesh ,  Hasnain Ahmad ,  Kok Wai Chan

IPC: H10N60/01 ,  H10N60/10

CPC classification number: H10N60/01 ,  H10N60/10

Abstract: This disclosure describes a superconducting device comprising a trench and a cavity that extends through a superconducting base layer. The trench crosses the cavity. The superconducting device further comprises a first junction layer that extends from a first region of the superconducting base layer to the cavity, an insulating layer on the surface of the first junction layer, and a second junction layer that extends from a second region of the superconducting base layer to the cavity. The second junction layer overlaps with the insulating layer on the bottom of the cavity. The disclosure also describes a method for producing this disclosed superconducting device.