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    Memory device
    61.
    发明授权
    Memory device 有权

    公开(公告)号：US11744088B2

    公开(公告)日：2023-08-29

    申请号：US17495103

    申请日：2021-10-06

    Applicant: Kioxia Corporation

    Inventor： Ryu Ogiwara ,  Daisaburo Takashima ,  Takahiko Iizuka

    IPC: G11C13/00 ,  H10B63/00 ,  H10N70/20 ,  H10N70/00

    CPC classification number: H10B63/845 ,  G11C13/0004 ,  G11C13/004 ,  H10B63/34 ,  H10N70/231 ,  H10N70/8828 ,  G11C2213/71 ,  G11C2213/79

    Abstract: According to one embodiment, a memory device includes: a first variable resistance layer; first and second semiconductor layers being in contact with the first variable resistance layer; a first word line; a second word line being adjacent to the first word line; and a third word line being adjacent to the first and second word lines with the first semiconductor layer, the first variable resistance layer, and the second semiconductor layer interposed therebetween, and provided between the first word line and the second word line. In the first variable resistance layer, a first region including a shortest path connecting the first word line and the third word line functions as a first memory cell, and a second region including a shortest path connecting the third word line and the second word line functions as a second memory cell.

    Capacitive pillar architecture for a memory array
    62.
    发明授权
    Capacitive pillar architecture for a memory array 有权

    公开(公告)号：US11729999B2

    公开(公告)日：2023-08-15

    申请号：US17735810

    申请日：2022-05-03

    Applicant: Micron Technology, Inc.

    Inventor： Innocenzo Tortorelli ,  Fabio Pellizzer

    IPC: G11C13/00 ,  H10B63/00 ,  H10N70/20

    CPC classification number: H10B63/845 ,  G11C13/003 ,  G11C13/0004 ,  H10B63/34 ,  H10N70/231 ,  G11C2213/71 ,  G11C2213/75

    Abstract: Methods, systems, and devices for a capacitive pillar architecture for a memory array are described. An access line within a memory array may be, include, or be coupled with a pillar. The pillar may include an exterior electrode, such as a hollow exterior electrode, surrounding an inner dielectric material that may further surround an interior, core electrode. The interior electrode may be maintained at a voltage level during at least a portion of an access operation for a memory cell coupled with the pillar. Such a pillar structure may increase a capacitance of the pillar, for example, based on a capacitive coupling between the interior and exterior electrodes. The increased capacitance may provide benefits associated with operating the memory array, such as increased memory cell programming speed, programming reliability, and read disturb immunity.

    MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
    67.
    发明公开
    MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20240365565A1

    公开(公告)日：2024-10-31

    申请号：US18306289

    申请日：2023-04-25

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Erh-Kun LAI ,  Feng-Min LEE

    IPC: H10B63/00 ,  H10B61/00

    CPC classification number: H10B63/34 ,  H10B61/22 ,  H10B63/845

    Abstract: A memory device and a method for manufacturing the same are provided. The memory device includes drain pillar structures, source pillar structures, memory structures surrounding the drain pillar structures respectively, a channel structure, and a gate structure surrounding the drain pillar structures, the source pillar structures and the channel structure. The channel structure is divided into arc channel parts by the drain pillar structures and the source pillar structures.

    Method for manufacturing memory device
    68.
    发明授权
    Method for manufacturing memory device 有权

    公开(公告)号：US12114514B2

    公开(公告)日：2024-10-08

    申请号：US18519230

    申请日：2023-11-27

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Feng-Min Lee ,  Erh-Kun Lai ,  Dai-Ying Lee ,  Yu-Hsuan Lin ,  Po-Hao Tseng ,  Ming-Hsiu Lee

    IPC: H10N50/01 ,  H10B61/00 ,  H10B63/00 ,  H10N70/00

    CPC classification number: H10B63/845 ,  H10B61/22 ,  H10B63/34 ,  H10N50/01 ,  H10N70/066

    Abstract: A memory device and a method for manufacturing the memory device are provided. The memory device includes a stack and a plurality of memory strings. The stack is disposed on the substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. The memory strings pass through the stack along a first direction, wherein a first memory string in the memory strings includes a first conductive pillar and a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar respectively extend along the first direction and are separated from each other. The channel layer is disposed between the first conductive pillar and the second conductive pillar. The memory structure surrounds the second conductive pillar, and the memory structure includes a resistive memory material.

    Semiconductor device including blocking pattern, electronic system, and method of forming the same
    69.
    发明授权
    Semiconductor device including blocking pattern, electronic system, and method of forming the same 有权

    公开(公告)号：US12082423B2

    公开(公告)日：2024-09-03

    申请号：US17679863

    申请日：2022-02-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyunmook Choi ,  Jooheon Kang ,  Sanghoon Kim ,  Jihong Kim

    IPC: H10B63/00

    CPC classification number: H10B63/34

    Abstract: A semiconductor device includes a horizontal wiring layer on a substrate, a stack structure disposed on the horizontal wiring layer and including insulating layers and electrode layers alternately stacked on each other, and a pillar structure extending into the horizontal wiring layer and extending through the stack structure. The electrode layers include one or a plurality of selection lines adjacent to an uppermost end of the stack structure, and word lines surrounding the stack structure below the one or plurality of selection lines. The pillar structure includes a variable resistive layer, a channel layer between the variable resistive layer and the stack structure, a gate dielectric layer between the channel layer and the stack structure, and a blocking pattern disposed between the variable resistive layer and the channel layer and being adjacent to a first selection line among the one or plurality of selection lines.

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