知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

291 条记录 (耗时 0.021 秒)

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    63.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
    半导体器件及制造半导体器件的方法

    公开(公告)号：US20160211173A1

    公开(公告)日：2016-07-21

    申请号：US15087427

    申请日：2016-03-31

    申请人： Renesas Electronics Corporation

    发明人： Yoshihiro Hayashi ,  Naoya INOUE ,  Kishou KANEKO

    IPC分类号： H01L21/768 ,  H01L29/66

    CPC分类号： H01L21/76807 ,  H01L21/28282 ,  H01L21/76877 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/24 ,  H01L29/242 ,  H01L29/41 ,  H01L29/42344 ,  H01L29/42352 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66757 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/792

    摘要： The method of manufacturing a semiconductor device, including preparing a semiconductor substrate, forming a first insulating layer over said semiconductor substrate, forming first grooves in the first insulating film, forming a gate electrode and a first interconnect in the first grooves, respectively, forming a gate insulating film over the gate electrode, forming a semiconductor layer over the gate insulating, forming a second insulating layer over the semiconductor layer and the first insulating film, forming a via in the second insulating layer, and forming a second interconnect such that the second interconnect is connected to the semiconductor layer through the via. The gate electrode, the first interconnect and the second interconnect are formed by Cu or Cu alloy, respectively.

    摘要翻译： 一种制造半导体器件的方法，包括制备半导体衬底，在所述半导体衬底上形成第一绝缘层，在第一绝缘膜中形成第一沟槽，分别在第一沟槽中形成栅电极和第一互连，形成 在所述栅电极上形成栅绝缘膜，在所述栅绝缘上形成半导体层，在所述半导体层和所述第一绝缘膜上形成第二绝缘层，在所述第二绝缘层中形成通孔，以及形成第二互连， 互连通过通孔连接到半导体层。 栅电极，第一互连和第二互连分别由Cu或Cu合金形成。

    3D NAND nonvolatile memory with staggered vertical gates
    64.
    发明授权
    3D NAND nonvolatile memory with staggered vertical gates 有权
    具有交错垂直门的3D NAND非易失性存储器

    公开(公告)号：US09349745B2

    公开(公告)日：2016-05-24

    申请号：US14555372

    申请日：2014-11-26

    申请人： Macronix International Co., Ltd.

    发明人： Hang-Ting Lue

    IPC分类号： H01L27/108 ,  H01L27/115 ,  H01L29/66 ,  H01L21/28 ,  H01L29/792 ,  H01L29/423 ,  H01L21/768 ,  H01L23/528 ,  G11C16/26 ,  G11C16/08

    CPC分类号： H01L27/11582 ,  G11C16/08 ,  G11C16/26 ,  H01L21/28282 ,  H01L21/76838 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42352 ,  H01L29/66833 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A memory device includes a plurality of stacks of conductive strips, a plurality of word lines over and orthogonal to the plurality of stacks of conductive strips, a plurality of vertical gate columns, and control circuitry. The plurality of word lines is electrically coupled to the plurality of vertical gate columns acting as gates controlling current flow in the plurality of stacks of conductive strips. The plurality of word lines including a first word line and a second word line adjacent to each other. The plurality of vertical gate columns is between the plurality of stacks of conductive strips. The plurality of vertical gate columns includes a first set of vertical gate columns electrically coupled to the first word line and a second set of vertical gate columns electrically coupled to the second word line. The first set of vertical gate columns is staggered relative to the second set of vertical gate columns. The control circuitry controls the plurality of word lines as gates to control current flow in the plurality of stacks of conductive strips, and controls nonvolatile memory operations.

    摘要翻译： 存储器件包括多个导电条的堆叠，多个字线在多个导体条的堆叠之上并且正交于多个堆叠的导电条，多个垂直栅极列和控制电路。 多个字线电耦合到多个垂直栅极柱，其用作控制多个导电条的堆叠中的电流的栅极。 多个字线包括彼此相邻的第一字线和第二字线。 多个垂直门柱位于多个导电片叠之间。 多个垂直门列包括电耦合到第一字线的第一组垂直栅极列和电耦合到第二字线的第二组垂直栅极列。 第一组垂直栅极列相对于第二组垂直栅极列交错。 控制电路控制多个字线作为门，以控制导电条的多个堆叠中的电流，并且控制非易失性存储器操作。

    Semiconductor device with buried gates and fabrication method thereof
    65.
    发明授权
    Semiconductor device with buried gates and fabrication method thereof 有权
    具有埋栅的半导体器件及其制造方法

    公开(公告)号：US09257436B2

    公开(公告)日：2016-02-09

    申请号：US13325552

    申请日：2011-12-14

    申请人： Jong-Han Shin

    发明人： Jong-Han Shin

    IPC分类号： H01L21/336 ,  H01L27/108 ,  H01L29/423

    CPC分类号： H01L29/4236 ,  H01L27/1052 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10894 ,  H01L29/42352 ,  H01L29/42356

    摘要： A semiconductor device includes a substrate having a cell region and a peripheral region, a buried gate formed over the substrate of the cell region, a peripheral gate formed over the substrate of the peripheral region and comprising a conductive layer, an inter-layer dielectric layer that covers the substrate, and a peripheral bit line formed inside the inter-layer dielectric layer and contacting the conductive layer.

    摘要翻译： 半导体器件包括具有单元区域和外围区域的衬底，形成在单元区域的衬底上的掩埋栅极，形成在周边区域的衬底上的外围栅极，并且包括导电层，层间电介质层 覆盖衬底以及形成在层间电介质层内部并与导电层接触的外围位线。

    NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
    67.
    发明申请
    NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US20150155360A1

    公开(公告)日：2015-06-04

    申请号：US14285085

    申请日：2014-05-22

    申请人： SK hynix Inc.

    发明人： Heon-Joon KIM ,  Jong-Hyun CHOI

    IPC分类号： H01L29/423 ,  H01L27/115 ,  H01L21/28

    CPC分类号： H01L21/28282 ,  H01L29/42352 ,  H01L29/66833 ,  H01L29/792

    摘要： A non-volatile memory device may include a first well of a first conductive type formed over a substrate, a second well of a second conductive type formed over the substrate to contact the first well, a trench formed over the substrate on a border formed by the contact of the first well and the second well, and a memory gate having a memory layer formed over a surface of the trench, and a gate electrode formed to fill the trench over the memory layer.

    摘要翻译： 非易失性存储器件可以包括在衬底上形成的第一导电类型的第一阱，形成在衬底上以接触第一阱的第二导电类型的第二阱，在衬底上形成的沟槽，该沟槽由 第一阱和第二阱的接触以及形成在沟槽的表面上的存储层的存储栅，以及形成为填充存储层上的沟槽的栅电极。

    Method of fabricating a three-dimentional semiconductor memory device
    70.
    发明授权
    Method of fabricating a three-dimentional semiconductor memory device 有权
    制造三维半导体存储器件的方法

    公开(公告)号：US08728893B2

    公开(公告)日：2014-05-20

    申请号：US13775453

    申请日：2013-02-25

    申请人： Samsung Electronics Co., Ltd.

    发明人： Byoungkeun Son ,  Jinho Kim ,  Hansoo Kim ,  Wonjun Lee ,  Daehyun Jang

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/42336 ,  H01L29/42352 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7827 ,  H01L29/7889 ,  H01L29/7926

    摘要： A method of fabricating a semiconductor memory device includes alternately and repeatedly stacking sacrificial layers and insulating layers on a substrate, forming an active pattern penetrating the sacrificial layers and the insulating layers, continuously patterning the insulating layers and the sacrificial layers to form a trench, removing the sacrificial layers exposed in the trench to form recess regions exposing a sidewall of the active pattern, forming an information storage layer on the substrate, forming a gate conductive layer on the information storage layer, such that the gate conductive layer fills the recess regions and defines an empty region in the trench, the empty region being surrounded by the gate conductive layer, and performing an isotropic etch process with respect to the gate conductive layer to form gate electrodes in the recess regions, such that the gate electrodes are separated from each other.

    摘要翻译： 一种制造半导体存储器件的方法包括在衬底上交替地和重复堆叠牺牲层和绝缘层，形成穿透牺牲层和绝缘层的有源图案，连续地图案化绝缘层和牺牲层以形成沟槽，去除 所述牺牲层暴露在所述沟槽中以形成暴露所述有源图案的侧壁的凹陷区域，在所述衬底上形成信息存储层，在所述信息存储层上形成栅极导电层，使得所述栅极导电层填充所述凹部区域， 在沟槽中限定空区域，空区域被栅极导电层包围，并且相对于栅极导电层执行各向同性蚀刻处理，以在凹陷区域中形成栅电极，使得栅电极与每个栅电极分离 其他。