公开(公告)号：US20170098691A1

公开(公告)日：2017-04-06

申请号：US15251881

申请日：2016-08-30

申请人： VIMICRO CORPORATION

发明人： Zhao Wang ,  Wenbo Tian ,  Hang Yin

IPC分类号： H01L49/02 ,  H01L21/8249 ,  H01L21/8222 ,  H01L27/06 ,  H01L21/8234

CPC分类号： H01L28/20 ,  H01L21/8221 ,  H01L27/0629 ,  H01L27/0647 ,  H01L27/0688 ,  H01L27/0705 ,  H01L27/0802

摘要： Techniques related to a method for manufacturing an integrated circuit is disclosed. According to one embodiment, a method for manufacturing an integrated circuit on a wafer comprises a first device of the integrated circuit is formed on the wafer and a second device of the integrated circuit is formed on the wafer to make a projection area of the second device overlap with a projection area of the first device partially or completely. In one embodiment, two or more devices are formed in different layers of the integrated circuit, or formed at different depths in a same layer of the integrated circuit, so the two or more devices may share an area on the same wafer in a certain manner. Thereby, the area of the chip is saved and the chip cost of the integrated circuit is significantly reduced.

公开(公告)号：US09490243B2

公开(公告)日：2016-11-08

申请号：US14419064

申请日：2012-08-22

申请人： Jean Philippe Laine ,  Patrice Besse

发明人： Jean Philippe Laine ,  Patrice Besse

IPC分类号： H01L27/02 ,  H01L21/8222 ,  H01L27/06 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L27/0259 ,  H01L21/8222 ,  H01L27/0255 ,  H01L27/0647 ,  H01L29/0649 ,  H01L29/1095

摘要： A semiconductor device is provided which comprises an ESD protection device. The ESD protection device is being formed by one or more pnp transistors which are present in the structure of the semiconductor device. The semiconductor device comprises two portions, of an isolated p-doped region which are separated by an N-doped region. Two p-doped regions are provided within the two portions. The p-dopant concentration of the two-doped region is higher than the p-dopant concentration of the isolated p-doped region. A first electrical contact is connected only via a highly doped p-contact region to the first p-doped region and a second electrical contact is connected only via another highly doped p-contact region to the second p-doped region.

摘要翻译： 提供一种包括ESD保护装置的半导体器件。 ESD保护器件由存在于半导体器件的结构中的一个或多个pnp晶体管形成。 半导体器件包括由N掺杂区域分离的隔离p掺杂区域的两个部分。 在两个部分内设置两个p掺杂区域。 双掺杂区域的p掺杂剂浓度高于分离的p掺杂区域的p掺杂剂浓度。 第一电接触仅通过高度掺杂的p接触区域连接到第一p掺杂区域，并且第二电触点仅通过另一个高度掺杂的p接触区域连接到第二p掺杂区域。

公开(公告)号：US09269616B2

公开(公告)日：2016-02-23

申请号：US14153848

申请日：2014-01-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd

发明人： Zhuo-Cang Yang ,  Chih-Kuan Chen

IPC分类号： H01L21/70 ,  H01L21/768 ,  H01L29/417 ,  H01L27/12 ,  H01L27/06

CPC分类号： H01L21/76877 ,  H01L21/743 ,  H01L21/761 ,  H01L21/76229 ,  H01L27/0629 ,  H01L27/0647 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/4175 ,  H01L29/7824 ,  H01L29/7835 ,  H01L29/8605 ,  H01L29/8611

摘要： Embodiments of a semiconductor device structure and a method of forming a semiconductor device structure are provided. The semiconductor device structure includes an insulating layer having a top surface, a bottom surface and a side surface. The semiconductor device structure also includes a first semiconductor substrate formed over the bottom surface of the first insulating layer. The semiconductor device structure further includes a conductive feature formed only adjacent to the side surface of the insulating layer on the first semiconductor substrate. In addition, the semiconductor device structure includes a second semiconductor substrate formed over the top surface of the insulating layer. The second semiconductor substrate includes a device-forming region formed directly over the insulating layer such that a projection region of the device-forming region is positioned inside the insulating layer.

摘要翻译： 提供半导体器件结构的实施例和形成半导体器件结构的方法。 半导体器件结构包括具有顶表面，底表面和侧表面的绝缘层。 半导体器件结构还包括形成在第一绝缘层的底表面上的第一半导体衬底。 半导体器件结构还包括仅在第一半导体衬底上与绝缘层的侧表面相邻形成的导电特征。 此外，半导体器件结构包括形成在绝缘层的顶表面上的第二半导体衬底。 第二半导体衬底包括直接在绝缘层上方形成的器件形成区域，使得器件形成区域的突出区域位于绝缘层的内部。

公开(公告)号：US20150221588A1

公开(公告)日：2015-08-06

申请号：US14688344

申请日：2015-04-16

申请人： International Rectifier Corporation

发明人： Mark Pavier ,  Daniel Cutler ,  Scott Palmer ,  Clive O'Dell ,  Rupert Burbidge

IPC分类号： H01L23/522 ,  H01L27/06

CPC分类号： H01L23/522 ,  H01L23/49811 ,  H01L25/072 ,  H01L25/18 ,  H01L27/0647 ,  H01L29/7393 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to an exemplary implementation, a power component includes a component substrate and a power semiconductor device electrically and mechanically coupled to the component substrate. The power component also includes at least one first peripheral contact and at least one second peripheral contact situated on the component substrate. A power semiconductor device is situated between the at least one first peripheral contact and the at least one second peripheral contact. The at least one first peripheral contact, the at least one second peripheral contact, and a surface electrode of the power semiconductor device are configured for surface mounting. The at least one first peripheral contact can be electrically coupled to the power semiconductor device.

摘要翻译： 根据示例性实施方式，功率部件包括电气和机械耦合到部件基板的部件基板和功率半导体器件。 功率部件还包括位于组件衬底上的至少一个第一外围接触件和至少一个第二外围触头。 功率半导体器件位于至少一个第一外围接触件和至少一个第二外围接触件之间。 功率半导体器件的至少一个第一周边接触件，至少一个第二外围接触件和表面电极被配置用于表面安装。 所述至少一个第一外围接触件可电耦合到功率半导体器件。

公开(公告)号：US20150200134A1

公开(公告)日：2015-07-16

申请号：US14153848

申请日：2014-01-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Zhuo-Cang YANG ,  Chih-Kuan CHEN

IPC分类号： H01L21/768 ,  H01L29/417 ,  H01L21/02 ,  H01L27/06

CPC分类号： H01L21/76877 ,  H01L21/743 ,  H01L21/761 ,  H01L21/76229 ,  H01L27/0629 ,  H01L27/0647 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/4175 ,  H01L29/7824 ,  H01L29/7835 ,  H01L29/8605 ,  H01L29/8611

摘要： Embodiments of a semiconductor device structure and a method of forming a semiconductor device structure are provided. The semiconductor device structure includes an insulating layer having a top surface, a bottom surface and a side surface. The semiconductor device structure also includes a first semiconductor substrate formed over the bottom surface of the first insulating layer. The semiconductor device structure further includes a conductive feature formed only adjacent to the side surface of the insulating layer on the first semiconductor substrate. In addition, the semiconductor device structure includes a second semiconductor substrate formed over the top surface of the insulating layer. The second semiconductor substrate includes a device-forming region formed directly over the insulating layer such that a projection region of the device-forming region is positioned inside the insulating layer.

摘要翻译： 提供半导体器件结构的实施例和形成半导体器件结构的方法。 半导体器件结构包括具有顶表面，底表面和侧表面的绝缘层。 半导体器件结构还包括形成在第一绝缘层的底表面上的第一半导体衬底。 半导体器件结构还包括仅在第一半导体衬底上与绝缘层的侧表面相邻形成的导电特征。 此外，半导体器件结构包括形成在绝缘层的顶表面上的第二半导体衬底。 第二半导体衬底包括直接在绝缘层上方形成的器件形成区域，使得器件形成区域的突出区域位于绝缘层的内部。

公开(公告)号：US20150076556A1

公开(公告)日：2015-03-19

申请号：US14372624

申请日：2012-01-20

申请人： Patrice Besse ,  Philippe Givelin ,  Eric Rolland

发明人： Patrice Besse ,  Philippe Givelin ,  Eric Rolland

IPC分类号： H01L27/02 ,  H01L29/74 ,  H01L27/06

CPC分类号： H01L27/0248 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/0647 ,  H01L29/7412 ,  H01L29/7428

摘要： An integrated circuit (IC) device including an electrostatic discharge (ESD) protection network for a high voltage application. The ESD protection network includes a common diode structure coupled between an external contact of the IC device and a substrate of the IC device, such that the common diode structure is forward biased towards the external contact, a Darlington transistor structure coupled between the external contact and the substrate of the IC device, and the Darlington transistor structure includes: an emitter node coupled to the external contact; a collector node coupled to the substrate; and a base node coupled between the emitter node of the Darlington transistor structure and the common diode structure. The at least one ESD protection network further comprises an isolation diode structure coupled between the emitter node and the base node of the Darlington transistor structure such that the isolation diode structure is forward biased towards the base node.

摘要翻译： 一种包括用于高电压应用的静电放电（ESD）保护网络的集成电路（IC）装置。 ESD保护网络包括耦合在IC器件的外部触点和IC器件的衬底之间的公共二极管结构，使得公共二极管结构朝向外部触点正向偏置，耦合在外部触点和 IC器件的衬底和达林顿晶体管结构包括：耦合到外部触点的发射极节点; 耦合到所述衬底的收集器节点; 以及耦合在达林顿晶体管结构的发射极节点和公共二极管结构之间的基极节点。 所述至少一个ESD保护网络还包括耦合在达林顿晶体管结构的发射极节点和基极节点之间的隔离二极管结构，使得隔离二极管结构向基极节点正向偏置。

公开(公告)号：US20130285210A1

公开(公告)日：2013-10-31

申请号：US13931599

申请日：2013-06-28

申请人： IXYS Corporation

发明人： Kyoung Wook Seok

IPC分类号： H01L27/06

CPC分类号： H01L25/0655 ,  H01L23/3107 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/5386 ,  H01L23/645 ,  H01L27/0647 ,  H01L27/0761 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/30107 ,  H02M7/003 ,  H02M7/04 ,  H01L2924/00014 ,  H01L2924/00

摘要： A full bridge rectifier includes four bipolar transistors, each of which has an associated parallel diode. A first pair of inductors provides inductive current splitting and thereby provides base current to/from one pair of the bipolar transistors so that the collector-to-emitter voltages of the bipolar transistors are low. A second pair of inductors similarly provides inductive current splitting to provide base current to/from the other pair of bipolar transistors. In one embodiment, all components are provided in a four terminal full bridge rectifier module. The module can be used as a drop-in replacement for a conventional four terminal full bridge diode rectifier. When current flows through the rectifier module, however, the voltage drop across the module is less than one volt. Due to the reduced low voltage drop, power loss in the rectifier module is reduced as compared to power loss in a conventional full bridge diode rectifier.

摘要翻译： 全桥整流器包括四个双极晶体管，每个具有相关的并联二极管。 第一对电感器提供感应电流分流，从而向一对双极晶体管提供基极电流，从而使双极晶体管的集电极到发射极的电压较低。 第二对电感器类似地提供感应电流分离以向/从另一对双极晶体管提供基极电流。 在一个实施例中，所有部件都设置在四端子全桥整流器模块中。 该模块可用作常规四端子全桥二极管整流器的插入式替代。 然而，当电流流过整流器模块时，模块上的电压降小于1伏。 由于降低的低压降，与传统的全桥二极管整流器中的功率损耗相比，整流器模块中的功率损耗降低。

公开(公告)号：US20130207730A1

公开(公告)日：2013-08-15

申请号：US13743667

申请日：2013-01-17

申请人： Electronics and Telecommunications Research Institute

发明人： Jongmin LEE ,  Byoung-Gue Min ,  Seong-Il Kim ,  Hyung Sup Yoon ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC分类号： H03H7/38 ,  H01G7/00 ,  H03F3/21

CPC分类号： H01L21/8222 ,  H01G7/00 ,  H01L27/0647 ,  H01L27/0658 ,  H01L29/93 ,  H03F1/565 ,  H03F3/21 ,  H03F2200/36 ,  H03F2200/378 ,  H03F2200/387 ,  H03F2200/391 ,  H03H7/38 ,  Y10T29/43

摘要： Disclosed is an impedance matching circuit capable of wideband matching. The impedance matching circuit includes: a first variable inductor unit of which one end is connected to the first node and an inductance value varies; a second inductor unit connected between the first node and a second node and having a variable inductance value; a first variable capacitor unit of which one end is connected to the first node and a capacitance value varies; and a second variable capacitor unit of which one end is connected to the second node and a capacitance value varies, and the other end of the first variable capacitor unit and the other end of the second variable capacitor unit are connected to a ground voltage terminal to perform the impedance matching between a circuit connected to the other end of the first variable inductor unit and a circuit connected to the second node.

摘要翻译： 公开了能够进行宽带匹配的阻抗匹配电路。 阻抗匹配电路包括：第一可变电感器单元，其一端连接到第一节点，电感值变化; 连接在第一节点和第二节点之间并具有可变电感值的第二电感器单元; 第一可变电容器单元，其一端连接到第一节点，电容值变化; 以及第二可变电容器单元，其一端连接到第二节点并且电容值变化，并且第一可变电容器单元的另一端和第二可变电容器单元的另一端连接到接地电压端子 执行连接到第一可变电感器单元的另一端的电路与连接到第二节点的电路之间的阻抗匹配。

公开(公告)号：US08502346B2

公开(公告)日：2013-08-06

申请号：US12928988

申请日：2010-12-23

申请人： Anup Bhalla

发明人： Anup Bhalla

IPC分类号： H01L27/06

CPC分类号： H01L27/0647 ,  H01L24/73 ,  H01L29/66348 ,  H01L29/7397 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/0557 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/32245 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012

摘要： This invention discloses a semiconductor power device formed in a semiconductor substrate. The semiconductor power device further includes a channel stop region near a peripheral of the semiconductor substrate wherein the channel stop region further includes a peripheral terminal of a diode corresponding with another terminal of the diode laterally opposite from the peripheral terminal disposed on an active area of the semiconductor power device. In an embodiment of this invention, the semiconductor power device is an insulated gate bipolar transistor (IGBT).

摘要翻译： 本发明公开了一种形成在半导体衬底中的半导体功率器件。 半导体功率器件还包括在半导体衬底的周边附近的通道停止区域，其中通道停止区域还包括二极管的外围端子，该二极管对应于二极管的另一个端子，该二极管的外部端子与设置在 半导体功率器件。 在本发明的一个实施例中，半导体功率器件是绝缘栅双极晶体管（IGBT）。

公开(公告)号：US20070241427A1

公开(公告)日：2007-10-18

申请号：US11686396

申请日：2007-03-15

申请人： Kazuhiro Mochizuki ,  Natsuki Yokoyama

发明人： Kazuhiro Mochizuki ,  Natsuki Yokoyama

IPC分类号： H01L31/00 ,  H01L29/739 ,  H01L27/082

CPC分类号： H01L21/8213 ,  H01L21/101 ,  H01L27/0647 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66068 ,  H01L29/6631 ,  H01L29/732 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49175 ,  H01L2924/00014

摘要： In conventional mesa-type npn bipolar transistors, the improvement of a current gain and the miniaturization of the transistor have been unachievable simultaneously as a result of a trade-off being present between lateral diffusion and recombination of the electrons which have been injected from an emitter layer into a base layer, and a high-density base contact region—emitter mesa distance. In contrast to the above, the present invention is provided as follows: The gradient of acceptor density in the depth direction of a base layer is greater at the edge of an emitter layer than at the edge of a collector layer. Also, the distance between a first mesa structure including the emitter layer and the base layer, and a second mesa structure including the base layer and the collector layer, is controlled to range from 3 μm to 9 μm. In addition, in order for the above to be implemented with high controllability, the base layer is formed of a first p-type base layer having an acceptor of uniform density, and a second p-type base layer whose density is greater than the uniform acceptor density of the first base layer while having a gradient in the depth direction of the second base layer. These features produce the advantageous effect that it is possible to provide a high-temperature adaptable, power-switching bipolar transistor that ensures a current gain high enough for practical use and is suitable for miniaturization.

摘要翻译： 在传统的台面型npn双极型晶体管中，由于在从发射极注入的电子的横向扩散和复合之间存在权衡的结果，电流增益的提高和晶体管的小型化是不可实现的 层到基层，以及高密度基极接触区域 - 发射极台面距离。 与上述相反，本发明提供如下：基底层的深度方向上的受主密度梯度在发射极层的边缘处比在集电极层的边缘处更大。 此外，包括发射极层和基底层的第一台面结构之间的距离和包括基底层和集电体层的第二台面结构的距离被控制在3μm到9μm的范围。 此外，为了实现上述的高可控性，基层由具有均匀密度的受体的第一p型基底层和密度大于均匀的第二p型基底层形成 同时具有第二基底层的深度方向上的梯度的第一基底层的受主密度。 这些特征产生有利的效果是可以提供高温适应性的功率开关双极晶体管，其确保电流增益足够高以用于实际应用并且适合于小型化。