公开(公告)号：US09761290B1

公开(公告)日：2017-09-12

申请号：US15247912

申请日：2016-08-25

Applicant: SanDisk Technologies LLC

Inventor： Navneeth Kankani ,  Ning Ye ,  Suresh Upadhyayula ,  Sarath Puthenthermadam ,  Deepanshu Dutta

IPC: G11C5/02 ,  G11C7/20 ,  H01L23/34 ,  H01L23/367 ,  H01L23/373 ,  H01L23/467 ,  G11C7/24

CPC classification number: G11C7/20 ,  G11C5/02 ,  G11C5/04 ,  G11C7/04 ,  G11C7/24 ,  G11C16/20 ,  G11C29/52 ,  G11C2029/0409 ,  H01L23/345 ,  H01L23/3675 ,  H01L23/3736 ,  H01L23/467 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/83805 ,  H01L2924/15311 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19105 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for preventing overheating, for annealing non-volatile memory. An apparatus may include an array of non-volatile storage elements. A heating element may be configured to heat a first set of the non-volatile storage elements to anneal the first set of non-volatile storage elements. A heat shield or cooling element may be configured to prevent a second set of the non-volatile storage elements from overheating during annealing of the first set of non-volatile storage elements, to mitigate data errors for data stored on the second set of non-volatile storage elements.

公开(公告)号：US09760437B2

公开(公告)日：2017-09-12

申请号：US14789055

申请日：2015-07-01

Applicant: International Business Machines Corporation

Inventor： Diyanesh B. Chinnakkonda Vidyapoornachary ,  Vijay Anand Mathiyalagan ,  Gary A. Tressler

IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06 ,  H03M13/35 ,  G11C7/04 ,  G11C29/04

CPC classification number: G06F11/1072 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/1048 ,  G11C7/04 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411 ,  H03M13/356

Abstract: Systems and methods to manage a memory device by executing program code to determine a temperature profile associated with a region of the memory device. The temperature profile may be one of many temperature profiles each associated with a respective region of the memory device. A correction capability may be determined based on the thermal profile and an error in the memory region may be corrected using the determined correction capability.

公开(公告)号：US09760136B2

公开(公告)日：2017-09-12

申请号：US14460533

申请日：2014-08-15

Applicant: Intel Corporation

Inventor： Thanunathan Rangarajan ,  Vinayak P. Risbud ,  Tabassum Yasmin

IPC: G06F12/00 ,  G06F1/20 ,  G11C7/04 ,  G11C29/20 ,  G11C29/46 ,  G11C29/00 ,  G11C5/04 ,  G11C29/04

CPC classification number: G06F1/206 ,  G06F11/3037 ,  G06F11/3058 ,  G11C5/04 ,  G11C7/04 ,  G11C29/20 ,  G11C29/46 ,  G11C29/52 ,  G11C29/76 ,  G11C2029/0407 ,  G11C2029/0409 ,  Y02D10/16

Abstract: In an embodiment, a processor includes at least one core to execute instructions and a memory controller coupled to the at least one core. In turn, the memory controller includes a spare logic to cause a dynamic transfer of data stored on a first memory device coupled to the processor to a second memory device coupled to the processor, responsive to a temperature of the first memory device exceeding a thermal threshold. Other embodiments are described and claimed.

公开(公告)号：US20170256297A1

公开(公告)日：2017-09-07

申请号：US15061732

申请日：2016-03-04

Applicant: Adesto Technologies Corporation

Inventor： Gideon Intrater ,  Bard Pedersen ,  Ishai Naveh

IPC: G11C8/06 ,  G11C7/22 ,  G11C7/10 ,  G11C7/06

CPC classification number: G11C8/06 ,  G11C5/066 ,  G11C7/062 ,  G11C7/103 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/22 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409 ,  G11C2029/5006

Abstract: A memory device can include: a memory array with memory cells arranged as data lines; an interface that receives a read command requesting bytes of data in a consecutively addressed order from an address of a starting byte; a first buffer that stores a first data line from the memory array that includes the starting byte; a second buffer that stores a second data line from the memory array, which is consecutively addressed with respect to the first data line; output circuitry configured to access data from the buffers, and to sequentially output each byte from the starting byte through a highest addressed byte of the first data line, and each byte from a lowest addressed byte of the second data line until the requested data bytes has been output; and a data strobe driver that clocks each byte of data output by a data strobe on the interface.

公开(公告)号：US20170255514A1

公开(公告)日：2017-09-07

申请号：US15280264

申请日：2016-09-29

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Mitsuaki HONMA

IPC: G06F11/10 ,  G11C16/10 ,  G06F3/06 ,  G11C16/16 ,  G11C29/52 ,  G11C16/26 ,  G11C16/04

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/0634 ,  G06F3/064 ,  G06F3/0647 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1048 ,  G11C7/1063 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C29/021 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: A memory system includes a semiconductor memory device having a memory cell array including a first area and a second area, and a controller configured to issue to the semiconductor memory device a first command designating reading of data from the first area using a first data reading scheme and a flag status associated with the data. If the flag status indicates the data is in a first state, the controller issues the second command to cause the data to be output from the semiconductor memory device to the controller. If the flag status indicates the data is in a second state, the controller issues the third command to cause the data to be transferred from the first area to the second area.

公开(公告)号：US20170242768A1

公开(公告)日：2017-08-24

申请号：US15215321

申请日：2016-07-20

Applicant: SK hynix Inc.

Inventor： Se Chun PARK ,  Ie Ryung PARK ,  Dong Kun AN ,  Na Ra CHO

IPC: G06F11/20 ,  G06F3/06

CPC classification number: G06F11/2069 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/0727 ,  G06F11/0751 ,  G06F11/1666 ,  G06F11/20 ,  G06F2201/805 ,  G11C29/76 ,  G11C29/78 ,  G11C2029/0409

Abstract: There are provided an electronic device, and more particularly, to a controller of a semiconductor memory device with an increased operation speed and a method of operating the same. The method of operating the controller configured to control the semiconductor memory device includes obtaining a recovery address in which recovered data stored in a page buffer of the semiconductor memory device in which the program fail is generated is to be stored, transmitting a recovery command requesting the semiconductor memory device to transmit the recovered data to the semiconductor memory device, and storing the recovered data in the recovery address. The obtaining of the recovery address, the transmitting of the recovery command, and the storing of the recovered data in the recovery address are simultaneously performed while a post-processing operation is performed on the program fail.

公开(公告)号：US20170236592A1

公开(公告)日：2017-08-17

申请号：US15496498

申请日：2017-04-25

Applicant: Seagate Technology LLC

Inventor： AbdelHakim S. Alhussien ,  Sundararajan Sankaranarayanan ,  Erich F. Haratsch

IPC: G11C16/26 ,  G11C29/50 ,  G06F11/10 ,  G11C16/34

CPC classification number: G11C16/26 ,  G06F11/00 ,  G06F11/10 ,  G06F11/1068 ,  G06F12/02 ,  G11C7/1006 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/28 ,  G11C16/3418 ,  G11C16/3431 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50004 ,  G11C29/50016 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2029/5004 ,  H03M13/05 ,  H03M13/1111 ,  H03M13/3746 ,  H03M13/6325

Abstract: A syndrome weight of failed decoding attempts is used to select parameters for future read retry operations. The following exemplary steps are performed until a decoding success or a predefined limited number of readings is reached: (i) reading a codeword using different read threshold voltages; (ii) mapping the readings to a corresponding likelihood value using a likelihood value assignment; and (iii) recording a syndrome weight for failed decoding attempts of the readings using the different read threshold voltages. Once the predefined limit is reached, the following exemplary steps are performed: (i) mapping the readings to a corresponding likelihood value using different likelihood value assignments, and (ii) recording a syndrome weight for failed decoding attempts of the readings using the different likelihood value assignments; and using a given read threshold voltage and/or a likelihood value assignment associated with a substantially minimum syndrome weight as an initial read threshold voltage and/or a higher priority read threshold voltage for subsequent read retry operations.

公开(公告)号：US20170229184A1

公开(公告)日：2017-08-10

申请号：US15239763

申请日：2016-08-17

Applicant: Winbond Electronics Corp.

Inventor： Kazuki Yamauchi

IPC: G11C16/14 ,  G11C16/34 ,  G11C29/52 ,  G11C29/44 ,  G06F11/10 ,  G11C16/04 ,  G11C16/26

CPC classification number: G11C16/14 ,  G06F11/1068 ,  G11C7/20 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/3459 ,  G11C29/42 ,  G11C29/44 ,  G11C29/52 ,  G11C2029/0409

Abstract: A semiconductor memory device, an erasing method and a programming method thereof which can improve yields and utilization efficiency of a memory array are provided. The semiconductor memory device includes a memory array, which includes a plurality of NAND strings; a page buffer/sensing circuit (170), which is connected to the NAND strings of the memory array through bit lines and outputs whether the NAND strings include failures; and a detecting circuit (200), which is connected to the plurality of page buffer/sensing circuits (170) and detects a number of the failures among the NAND strings of a selected block. The block is determined to be usable when the number of the failures among the NAND strings detected by the detecting circuit (200) is less than or equal to a fixed number, and the block is determined to be unusable as a bad block when the number of the failures exceeds the fixed number.

公开(公告)号：USRE46498E1

公开(公告)日：2017-08-01

申请号：US14230883

申请日：2014-03-31

Applicant: SanDisk Technologies Inc.

Inventor： Deepak Chandra Sekar ,  Nima Mokhlesi

IPC: G11C16/04 ,  G11C5/14 ,  G11C16/10 ,  G11C16/26 ,  G11C29/04

CPC classification number: G11C5/146 ,  G11C16/10 ,  G11C16/26 ,  G11C2029/0409

Abstract: Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased or decreased as a number of programming cycles increases. Also, body bias levels can be set and applied separately for a chip, plane, block and/or page. A body bias can be applied to a first set of NAND strings for which operations are being performed by controlling a first voltage provided to a source side of the first set of NAND strings and a second voltage provided to a p-well. A source side of a second set of NAND strings for which operations are not being performed is floated or receives a fixed voltage.

公开(公告)号：US20170206953A1

公开(公告)日：2017-07-20

申请号：US15172162

申请日：2016-06-03

Applicant: VIA Technologies, Inc.

Inventor： Ying Yu Tai ,  Jiangli Zhu

IPC: G11C11/56 ,  G11C16/34 ,  G11C29/52 ,  G11C16/26

CPC classification number: G11C11/5642 ,  G06F11/1072 ,  G11C16/26 ,  G11C16/3427 ,  G11C29/52 ,  G11C2029/0409

Abstract: A non-volatile memory apparatus includes a non-volatile storage circuit and a controller. The non-volatile storage circuit reads a corresponding data voltage set, and converts the corresponding data voltage set to the corresponding data in accordance with the read-voltage parameter of the controller. The controller decides whether to perform the on-the-fly self-adaptive read-voltage adjustment in accordance with the number of error bits of the corresponding data. The on-the-fly self-adaptive read-voltage adjustment includes: providing a left (or lower) read-voltage parameter to the non-volatile storage circuit for converting the corresponding data voltage set to the left corresponding data; providing a right (or higher) read-voltage parameter to the non-volatile storage circuit for converting the corresponding data voltage set to the right corresponding data; and deciding the adjusting-direction and the adjusting-amount of the read-voltage parameter in accordance with the relationship between the corresponding data, the left corresponding data and the right corresponding data.