公开(公告)号：US09983793B2

公开(公告)日：2018-05-29

申请号：US15712296

申请日：2017-09-22

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Lei Liu ,  Chengyong Wu ,  Xiaobing Feng

IPC: G06F3/06 ,  G06F11/34 ,  G06F9/50 ,  G06F12/0811 ,  G06F12/0842 ,  G06F12/0897 ,  G06F12/084

CPC classification number: G06F3/0605 ,  G06F3/0631 ,  G06F3/0644 ,  G06F3/0653 ,  G06F3/0679 ,  G06F9/5016 ,  G06F11/3409 ,  G06F11/3433 ,  G06F11/3471 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0897 ,  G06F2201/81 ,  G06F2212/1041 ,  G06F2212/282 ,  G06F2212/6042 ,  G06F2212/653

Abstract: Embodiments of the present invention provide a memory resource optimization method and apparatus, relate to the computer field, solve a problem that existing multi-level memory resources affect each other, and optimize an existing single partitioning mechanism. A specific solution is: obtaining performance data of each program in a working set by using a page coloring technology, obtaining a category of each program in light of a memory access frequency, selecting, according to the category of each program, a page coloring-based partitioning policy corresponding to the working set, and writing the page coloring-based partitioning policy to an operating system kernel, to complete corresponding page coloring-based partitioning processing. The present invention is used to eliminate or reduce mutual interference of processes or threads on a memory resource in light of a feature of the working set, thereby improving overall performance of a computer.

公开(公告)号：US20180136998A1

公开(公告)日：2018-05-17

申请号：US15871452

申请日：2018-01-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Christian Habermann ,  Gerrit Koch ,  Martin Recktenwald ,  Ralf Winkelmann

IPC: G06F11/07 ,  G06F11/14 ,  G06F11/22 ,  G06F12/0897 ,  G06F12/0891 ,  G06F12/0875 ,  G06F12/0842 ,  G06F12/0815 ,  G06F12/0811 ,  G06F12/0808 ,  G06F11/26

CPC classification number: G06F11/0724 ,  G06F11/141 ,  G06F11/1474 ,  G06F11/2242 ,  G06F11/261 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0837 ,  G06F12/0842 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/0897 ,  G06F2212/1032 ,  G06F2212/452 ,  G06F2212/6042 ,  G06F2212/621

Abstract: Testing a data coherency algorithm of a multi-processor environment. The testing includes implementing a global time incremented every processor cycle and used for timestamping; implementing a transactional execution flag representing a processor core guaranteeing the atomicity and coherency of the currently executed instructions; implementing a transactional footprint, which keeps the address of each cache line that was used by the processor core; implementing a reference model, which operates on every cache line and keeps a set of timestamps for every cache line; implementing a core observed timestamp representing a global timestamp, which is the oldest construction date of data used before; implementing interface events; and reporting an error whenever a transaction end event is detected and any cache line is found in the transactional footprint with an expiration date that is older than or equal to the core observed time.

公开(公告)号：US09959155B2

公开(公告)日：2018-05-01

申请号：US15197534

申请日：2016-06-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Christian Habermann ,  Gerrit Koch ,  Martin Recktenwald ,  Ralf Winkelmann

IPC: G06F11/00 ,  G06F11/07 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0842 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/0897 ,  G06F11/22 ,  G06F11/14 ,  G06F11/26

CPC classification number: G06F11/0724 ,  G06F11/141 ,  G06F11/1474 ,  G06F11/2242 ,  G06F11/261 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0842 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/0897 ,  G06F2212/1032 ,  G06F2212/452 ,  G06F2212/6042 ,  G06F2212/621

Abstract: Testing a data coherency algorithm of a multi-processor environment. The testing includes implementing a global time incremented every processor cycle and used for timestamping; implementing a transactional execution flag representing a processor core guaranteeing the atomicity and coherency of the currently executed instructions; implementing a transactional footprint, which keeps the address of each cache line that was used by the processor core; implementing a reference model, which operates on every cache line and keeps a set of timestamps for every cache line; implementing a core observed timestamp representing a global timestamp, which is the oldest construction date of data used before; implementing interface events; and reporting an error whenever a transaction end event is detected and any cache line is found in the transactional footprint with an expiration date that is older than or equal to the core observed time.

公开(公告)号：US09940246B1

公开(公告)日：2018-04-10

申请号：US15288815

申请日：2016-10-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bernard C. Drerup ,  Ram Raghavan ,  Sahil Sabharwal ,  Jeffrey A. Stuecheli

IPC: G06F12/08 ,  G06F12/0891 ,  G06F12/0864 ,  G06F12/0897

CPC classification number: G06F12/0897 ,  G06F12/0864 ,  G06F12/122 ,  G06F12/128 ,  G06F2212/60

Abstract: In one embodiment, a set-associative cache memory has a plurality of congruence classes each including multiple entries for storing cache lines of data. The cache memory includes a bank of counters, which includes a respective one of a plurality of counters for each cache line stored in the plurality of congruence classes. The cache memory selects victim cache lines for eviction from the cache memory by reference to counter values of counters within the bank of counters. A dynamic distribution of counter values of counters within the bank of counters is determined. In response, an amount counter values of counters within the bank of counters are adjusted on a cache miss is adjusted based on the dynamic distribution of the counter values.

公开(公告)号：US20180089107A1

公开(公告)日：2018-03-29

申请号：US15712418

申请日：2017-09-22

Applicant: EMC IP Holding Company LLC

Inventor： Bob Yan ,  Bernie Hu ,  Vincent Wu ,  Jia Huang ,  Amber Li

IPC: G06F12/123 ,  G06F12/127 ,  G06F12/0866 ,  G06F12/02 ,  G06F3/06

CPC classification number: G06F12/123 ,  G06F3/064 ,  G06F12/0246 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0868 ,  G06F12/0897 ,  G06F12/127 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/461 ,  G06F2212/466 ,  G06F2212/6024

Abstract: The present disclosure provided a method, apparatus, and system for caching data. In an embodiment of the present disclosure, the method for caching data comprises: recording, within a recording period for recording access count information of the data, access count information on respective data, wherein the recording period includes a plurality of recording timeslots, wherein the recording of the access count information within a single recording timeslot is restricted, while the access count information within the plurality of recording timeslots is aggregated; and promoting, in response to expiration of the recording period, the respective data into a cache area based on the access count information.

公开(公告)号：US20180081818A1

公开(公告)日：2018-03-22

申请号：US15268974

申请日：2016-09-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Shuai Che ,  Jieming Yin

IPC: G06F12/0897

CPC classification number: G06F12/0897 ,  G06F2212/1024 ,  G06F2212/60

Abstract: A method and apparatus for transmitting data includes determining whether to apply a mask to a cache line that includes a first type of data and a second type of data for transmission based upon a first criteria. The second type of data is filtered from the cache line, and the first type of data along with an identifier of the applied mask is transmitted. The first type of data and the identifier is received, and the second type of data is combined with the first type of data to recreate the cache line based upon the received identifier.

公开(公告)号：US09921961B2

公开(公告)日：2018-03-20

申请号：US15400122

申请日：2017-01-06

Applicant: Intel Corporation

Inventor： Christopher B. Wilkerson ,  Alaa R. Alameldeen ,  Zhe Wang ,  Zeshan A. Chishti

IPC: G11C16/04 ,  G06F12/0804 ,  G06F12/12

CPC classification number: G06F12/0804 ,  G06F12/0292 ,  G06F12/0868 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/12 ,  G06F2212/1021 ,  G06F2212/502 ,  G06F2212/608 ,  G06F2212/651 ,  G11C8/00 ,  G11C11/56 ,  G11C16/08

Abstract: A multi-level memory management circuit can remap data between near and far memory. In one embodiment, a register array stores near memory addresses and far memory addresses mapped to the near memory addresses. The number of entries in the register array is less than the number of pages in near memory. Remapping logic determines that a far memory address of the requested data is absent from the register array and selects an available near memory address from the register array. Remapping logic also initiates writing of the requested data at the far memory address to the selected near memory address. Remapping logic further writes the far memory address to an entry of the register array corresponding to the selected near memory address.

公开(公告)号：US20180067679A1

公开(公告)日：2018-03-08

申请号：US15259686

申请日：2016-09-08

Applicant: QUALCOMM Incorporated

Inventor： Mattheus Cornelius Antonius Adrianus Heddes ,  Perry Willmann Remaklus, JR.

IPC: G06F3/06 ,  G06F12/0897

CPC classification number: G06F3/0638 ,  G06F3/0613 ,  G06F3/0626 ,  G06F3/0673 ,  G06F12/0897 ,  G06F13/1668 ,  G06F2212/60 ,  H03M7/3066 ,  H03M7/3086 ,  H03M7/70

Abstract: Providing efficient lossless compression for small data blocks in processor-based systems is provided. In one aspect, a method comprises receiving a plurality of input words. Each mask of a plurality of masks is applied to each unassigned input word to generate a corresponding plurality of patterns. For each mask, if a most frequently occurring pattern exists among the plurality of patterns, the most frequently occurring pattern and an uncompressed data portion of each unassigned input word are stored in association with a prefix associated with the mask. The prefix is also assigned to each unassigned input word corresponding to the most frequently occurring pattern. A compressed output block is generated, comprising prefixes assigned to the plurality of input words, the most frequently occurring patterns associated with the assigned prefixes, and uncompressed data portions corresponding to one or more input words of the plurality of input words.

公开(公告)号：US09910605B2

公开(公告)日：2018-03-06

申请号：US15353431

申请日：2016-11-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Nuwan S. Jayasena ,  Gabriel H. Loh ,  James M. O'Connor ,  Niladrish Chatterjee

IPC: G06F3/06 ,  G06F12/06 ,  G06F12/0811

CPC classification number: G06F3/0613 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/0647 ,  G06F3/0685 ,  G06F12/0292 ,  G06F12/0638 ,  G06F12/0811 ,  G06F12/0897 ,  G06F2212/205 ,  G11C11/005 ,  Y02D10/13

Abstract: A die-stacked hybrid memory device implements a first set of one or more memory dies implementing first memory cell circuitry of a first memory architecture type and a second set of one or more memory dies implementing second memory cell circuitry of a second memory architecture type different than the first memory architecture type. The die-stacked hybrid memory device further includes a set of one or more logic dies electrically coupled to the first and second sets of one or more memory dies, the set of one or more logic dies comprising a memory interface and a page migration manager, the memory interface coupleable to a device external to the die-stacked hybrid memory device, and the page migration manager to transfer memory pages between the first set of one or more memory dies and the second set of one or more memory dies.

公开(公告)号：US20180052606A1

公开(公告)日：2018-02-22

申请号：US15243446

申请日：2016-08-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： BRADLY G. FREY ,  GUY L. GUTHRIE ,  CATHY MAY ,  WILLIAM J. STARKE ,  DEREK E. WILLIAMS

IPC: G06F3/06 ,  G06F12/0897 ,  G06F13/16 ,  G06F13/40 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F3/065 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0673 ,  G06F9/3004 ,  G06F9/3836 ,  G06F12/0897 ,  G06F13/1689 ,  G06F13/4068 ,  G06F2212/60

Abstract: In a data processing system implementing a weak memory model, a lower level cache receives, from a processor core, a plurality of copy-type requests and a plurality of paste-type requests that together indicate a memory move to be performed. The lower level cache also receives, from the processor core, a barrier request that requests enforcement of ordering of memory access requests prior to the barrier request with respect to memory access requests after the barrier request. In response to the barrier request, the lower level cache enforces a barrier indicated by the barrier request with respect to a final paste-type request ending the memory move but not with respect to other copy-type requests and paste-type requests in the memory move.