公开(公告)号：US11537519B1

公开(公告)日：2022-12-27

申请号：US17389012

申请日：2021-07-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Derek E. Williams ,  Guy L. Guthrie ,  Hugh Shen ,  David Campbell ,  Bryan Lloyd ,  Samuel David Kirchhoff ,  Jeffrey A. Stuecheli

IPC: G06F12/0811 ,  G06F12/0808 ,  G06F12/02 ,  G06F12/1045 ,  G06F12/0817

Abstract: A memory-referent instruction is executed to calculate a target effective address (EA) of a corresponding memory-referent request. An array entry in an upper level cache is allocated, and the EA is specified in a corresponding EA directory entry. While in-flight, the memory-referent request is buffered in a queue in association with a pointer to the entry in the EA directory. Based on receiving a translation invalidation request requesting invalidation of an address translation in a translation structure, the processor core walks the EA directory, determines the EA in the entry matches an address range specified by the translation invalidation request, and, based on the match, precisely marks the memory-referent request using the pointer to the EA directory entry. Based on the marking, the translation invalidation request is permitted to complete with reference to the processor core only after the memory-referent request has drained from the processing unit.

公开(公告)号：US11269561B2

公开(公告)日：2022-03-08

申请号：US17129248

申请日：2020-12-21

Applicant: International Business Machines Corporation

Inventor： Jie Zheng ,  Steven R. Carlough ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Stephen J. Powell

IPC: G06F3/06 ,  G06F9/38 ,  G06F9/52

Abstract: A system and associated processes may perform a memory access operation that includes receiving a data packet comprising a command of a type of a plurality of types of commands. The processes may include initiating a decoding of a first portion of the command, and automatically speculating as to the type of the command. Based on the speculation as to the type of the command, a bank activate command may be generated before the data packet is entirely decoded or received.

公开(公告)号：US11030110B2

公开(公告)日：2021-06-08

申请号：US16395942

申请日：2019-04-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael S. Siegel ,  Bartholomew Blaner ,  Jeffrey A. Stuecheli ,  William J. Starke ,  Derek E. Williams ,  Kenneth M. Valk ,  John D. Irish ,  Lakshminarayana Arimilli

IPC: G06F12/10 ,  G06F13/16 ,  G06F9/38 ,  G06F12/0817 ,  G06F12/1027 ,  G06F12/1045 ,  G06F3/06 ,  G06F13/28 ,  G06F9/455

Abstract: An integrated circuit includes a first communication interface for communicatively coupling the integrated circuit with a coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from a system memory, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory. The integrated circuit further includes request logic that communicates memory access requests and request responses with the accelerator unit. The request logic, responsive to receipt from the accelerator unit of a read-type request specifying an aliased second effective address of a target cache line, provides a request response including a host tag indicating that the accelerator unit has associated a different first effective address with the target cache line.

公开(公告)号：US10884943B2

公开(公告)日：2021-01-05

申请号：US16117099

申请日：2018-08-30

Applicant: International Business Machines Corporation

Inventor： Bartholomew Blaner ,  Jay G. Heaslip ,  Robert D. Herzl ,  Jody B. Joyner ,  Jeffrey A. Stuecheli

IPC: G06F12/02 ,  G06F12/0897 ,  G06F12/1009

Abstract: A method, computer program product, and a computer system are disclosed for processing information in a processor that in one or more embodiments includes setting a threshold number of free Effective to Real Address Translation (ERAT) cache entries in an ERAT cache; determining whether a total number of free ERAT cache entries is less than or equal to the threshold number of free ERAT cache entries; allocating, in response to determining that the total number of free entries is less than or equal to the threshold number, one or more active ERAT cache entries to be speculatively checked in to a memory management unit (MMU); and speculatively checking in the one or more active ERAT cache entries to the MMU.

公开(公告)号：US10831889B2

公开(公告)日：2020-11-10

申请号：US16539537

申请日：2019-08-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： William E. Hall ,  Guerney D. H. Hunt ,  Ronald N. Kalla ,  Jentje Leenstra ,  Paul Mackerras ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC: G06F21/00 ,  G06F21/55 ,  G06F9/455 ,  G06F21/53 ,  G06F12/14 ,  G06F13/40 ,  G06F13/364 ,  G06F21/78 ,  G06F21/62

Abstract: A system, a method, and a computer program product for secure memory implementation for secure execution of virtual machines are provided. Data is processed in a first mode and a second mode, and commands are sent to a chip interconnect bus using real addresses, wherein the chip interconnect bus transports a number of bits for the real addresses. A memory controller is operatively coupled to a memory component. A secure memory range is specified by using range registers. If the real address is detected to be in the secure memory range to match a memory component address, a real address bit is set. If the real address is in the memory address hole, a security access violation is detected. If the real address is not in the secure address range and the real address bit is set, the security access violation is detected.

公开(公告)号：US10437725B2

公开(公告)日：2019-10-08

申请号：US15667330

申请日：2017-08-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Guy L. Guthrie ,  Michael S. Siegel ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC: G06F12/08 ,  G06F12/0831 ,  G06F12/0891 ,  G06F12/0811 ,  G06F12/0897 ,  G06F12/0815

Abstract: A technique for operating a data processing system includes transitioning, by a cache, to a highest point of coherency (HPC) for a cache line in a required state without receiving data for one or more segments of the cache line that are needed. The cache issues a command to a lowest point of coherency (LPC) that requests data for the one or more segments of the cache line that were not received and are needed. The cache receives the data for the one or more segments of the cache line from the LPC that were not previously received and were needed.

公开(公告)号：US10216653B2

公开(公告)日：2019-02-26

申请号：US15723949

申请日：2017-10-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Lakshminarayana Baba Arimilli ,  Yiftach Benjamini ,  Bartholomew Blaner ,  Daniel M. Dreps ,  John David Irish ,  David J. Krolak ,  Lonny Lambrecht ,  Michael S. Siegel ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Kenneth M. Valk ,  Curtis C. Wollbrink

IPC: G06F13/16 ,  G06F13/42 ,  G06F3/06

Abstract: A serial communication system includes a transmitting circuit for serially transmitting data via a serial communication link including N channels where N is an integer greater than 1. The transmitting circuit includes an input buffer having storage for input data frames each including M bytes forming N segments of M/N contiguous bytes. The transmitting circuit additionally includes a reordering circuit coupled to the input buffer. The reordering circuit includes a reorder buffer including multiple entries. The reordering circuit buffers, in each of multiple entries of the reorder buffer, a byte in a common byte position in each of the N segments of an input data frame. The reordering circuit sequentially outputs the contents of the entries of the reorder buffer via the N channels of the serial communication link.

公开(公告)号：US09892066B1

公开(公告)日：2018-02-13

申请号：US15339465

申请日：2016-10-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John S. Dodson ,  Didier R. Louis ,  Eric E. Retter ,  Jeffrey A. Stuecheli

IPC: G06F13/00 ,  G06F13/16 ,  G06F3/06 ,  G06F13/38

CPC classification number: G06F13/1642 ,  G06F3/0608 ,  G06F3/0653 ,  G06F3/0685 ,  G06F13/38

Abstract: A memory system comprises a memory device coupled to a memory controller, the memory controller for receiving one or more memory requests from one or more core devices via an interconnect bus. The memory controller tracks utilization of the interconnect bus by tracking a selection of the one or more memory requests with fetched data from the one or more memory devices and waiting for scheduling to return on the interconnect bus during a time window. The memory controller, responsive to detecting utilization of the interconnect bus during the time window reaches a memory utilization threshold, dynamically selects a reduced read data size for a size of the fetched data to be returned with at least one read request from among the selection of one or more memory requests, the reduced data size selected from among at least two read data size options for the at least one read request of a maximum read data size and the reduced read data size that is less than the maximum read data size.

公开(公告)号：US09727489B1

公开(公告)日：2017-08-08

申请号：US15288767

申请日：2016-10-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bernard C. Drerup ,  Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC: G06F12/12 ,  G06F12/08 ,  G06F12/128 ,  G06F12/0864 ,  G06F12/0811 ,  G06F12/0831

CPC classification number: G06F12/128 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0833 ,  G06F12/0864 ,  G06F2212/1008 ,  G06F2212/283 ,  G06F2212/6032 ,  G06F2212/621

Abstract: A set-associative cache memory includes a plurality of congruence classes each including multiple entries for storing cache lines of data. A respective one of a plurality of counters is maintained for each cache line stored in the multiple entries. In response to a memory access request, the cache memory selects a victim cache line stored in a particular entry of a particular congruence class for eviction from the cache memory by reference to at least a counter value of the victim cache line. The cache memory also receives a new cache line of data for insertion into the particular entry and an indication of a distance from the cache memory to a data source from which the cache memory received the new cache line. The cache memory installs the new cache line in the particular entry and sets an initial counter value of the counter for the new cache line based on the received indication of the distance.

公开(公告)号：US09684461B1

公开(公告)日：2017-06-20

申请号：US15339406

申请日：2016-10-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John S. Dodson ,  Stephen J. Powell ,  Eric E. Retter ,  Jeffrey A. Stuecheli

IPC: G06F12/00 ,  G06F3/06 ,  G06F13/42

CPC classification number: G06F3/0613 ,  G06F3/0634 ,  G06F3/0653 ,  G06F3/0658 ,  G06F3/0673 ,  G06F13/1668 ,  G06F13/4234

Abstract: A memory system comprises memory devices coupled to a memory controller via a memory interface bus, the memory controller for receiving one or more memory requests via an interconnect. The memory controller tracks utilization of the memory interface bus for reads from the memory devices for a selection of the one or more memory requests during a time window. The memory controller, responsive to detecting utilization of the memory interface bus for reads during the time window reaches a memory utilization threshold, dynamically selects a reduced read data size for a size of data to be accessed from the memory devices by at least one read operation, the reduced data size selected from among at least two read data size options for the at least one read operation of a maximum read data size and the reduced read data size that is less than the maximum read data size.